occheung 8da924ec0f dma: set conversion granularity using bus width		2021-11-08 16:59:08 +08:00
..
phy	Merge pull request #1774 from m-labs/fastino-cic	2021-10-28 17:44:20 +02:00
sed	gateware,runtime: optimize RTIO kernel interface further	2018-11-08 18:29:24 +08:00
__init__.py	cri: fix firmware routing table access	2018-09-12 18:08:16 +08:00
analyzer.py	dma: set conversion granularity using bus width	2021-11-08 16:59:08 +08:00
cdc.py	rtio: use BlindTransfer from Migen	2019-07-05 18:46:18 +08:00
channel.py	use FutureWarning instead of DeprecationWarning	2018-10-21 12:14:51 +08:00
core.py	rtio: use BlindTransfer from Migen	2019-07-05 18:46:18 +08:00
cri.py	rtio: remove legacy i_overflow_reset CSR	2020-08-06 17:52:32 +08:00
dma.py	dma: set conversion granularity using bus width	2021-11-08 16:59:08 +08:00
input_collector.py	rtio: use BlindTransfer from Migen	2019-07-05 18:46:18 +08:00
moninj.py	moninj: do not require a rsys clock domain	2017-02-20 15:52:48 +08:00
rtlink.py	rtlink: sanity-check parameters	2018-11-26 01:14:02 +08:00
tsc.py	add missing files	2018-09-05 16:09:02 +08:00
xilinx_clocking.py	gateware: share RTIOClockMultiplier and fix_serdes_timing_path (#1760)	2021-10-07 08:19:38 +08:00