Robert Jordens 2f1029c292 Revert "sawg: advance dds 1/2 by one sample group" ... This reverts commit 8e0a1cbdc8. c.f. #772 The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.		2017-07-04 17:55:19 +02:00
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amp	firmware: don't build libdyld through misoc.	2017-03-14 08:33:31 +00:00
drtio	drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times	2017-06-21 17:01:52 +08:00
dsp	Revert "sawg: advance dds 1/2 by one sample group"	2017-07-04 17:55:19 +02:00
rtio	artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect	2017-07-04 10:48:06 +02:00
targets	sawg: stage code for y-data exchange on channels	2017-06-22 10:26:29 +02:00
test	sawg: also give offset some headroom	2017-07-04 16:50:06 +02:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9_dds.py	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
ad9154_fmc_ebz.py	Merge remote-tracking branch 'm-labs/phaser2' into phaser2	2016-12-02 14:11:56 +01:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
spi.py	spi: fix xfers with full data_width (closes #615)	2017-01-03 19:51:14 +01:00