Assume that rt2wb transactions either collide and are then
reported (https://github.com/m-labs/artiq/issues/308) or that
they complete and the delay with which they complete does not matter.
If a transaction is ack'ed with a delay because the WB core's downstream
logic is busy, that may lead to a later collision with another WB
transaction.
perl -i -pe 's/^from artiq import \*$/from artiq.experiment import */' your_experiments/*.py
(assuming you skipped the changes form the previous commit)
