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rtio: collision_error -> collision

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This commit is contained in:
Sebastien Bourdeauducq 2016-03-08 15:38:08 +08:00
parent 59d7f5f1e3
commit 71105fd0d7
9 changed files with 27 additions and 25 deletions
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2
RELEASE_NOTES.rst
View File

@ -10,3 +10,5 @@ Release notes
* Core device flash storage has moved due to increased runtime size.
This requires reflashing the runtime and the flash storage filesystem image
or erase and rewrite its entries.
* RTIOCollisionError has been renamed to RTIOCollision

4
artiq/coredevice/__init__.py
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@ -1,12 +1,12 @@
from artiq.coredevice import exceptions, dds, spi
from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError,
RTIOCollisionError, RTIOOverflow,
RTIOCollision, RTIOOverflow,
DDSBatchError, CacheError)
from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,
PHASE_MODE_TRACKING)
__all__ = []
__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollisionError",
__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollision",
"RTIOOverflow", "DDSBatchError", "CacheError"]
__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",
"PHASE_MODE_TRACKING"]

2
artiq/coredevice/exceptions.py
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@ -86,7 +86,7 @@ class RTIOSequenceError(Exception):
"""
artiq_builtin = True
class RTIOCollisionError(Exception):
class RTIOCollision(Exception):
"""Raised when an event is submitted on a given channel with the same
coarse timestamp as the previous one but with a different fine timestamp.

2
artiq/gateware/rtio/analyzer.py
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@ -82,7 +82,7 @@ class MessageEncoder(Module, AutoCSR):
rtio_core.counter.value_sys << rtio_core.fine_ts_width),
]
for ename in ("o_underflow_reset", "o_sequence_error_reset",
"o_collision_error_reset", "i_overflow_reset"):
"o_collision_reset", "i_overflow_reset"):
self.comb += \
If(getattr(kcsrs, ename).re,
exception_stb.eq(1),

22
artiq/gateware/rtio/core.py
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@ -103,7 +103,7 @@ class _OutputManager(Module):
self.underflow = Signal() # valid 1 cycle after we, pulsed
self.sequence_error = Signal()
self.collision_error = Signal()
self.collision = Signal()
# # #
@ -126,7 +126,7 @@ class _OutputManager(Module):
# Special cases
replace = Signal()
sequence_error = Signal()
collision_error = Signal()
collision = Signal()
any_error = Signal()
nop = Signal()
self.sync.rsys += [
@ -140,10 +140,10 @@ class _OutputManager(Module):
< buf.timestamp[fine_ts_width:])
]
if fine_ts_width:
self.sync.rsys += collision_error.eq(
self.sync.rsys += collision.eq(
(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
& (self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width]))
self.comb += any_error.eq(sequence_error | collision_error)
self.comb += any_error.eq(sequence_error | collision)
if interface.suppress_nop:
# disable NOP at reset: do not suppress a first write with all 0s
nop_en = Signal(reset=0)
@ -163,7 +163,7 @@ class _OutputManager(Module):
]
self.comb += [
self.sequence_error.eq(self.we & sequence_error),
self.collision_error.eq(self.we & collision_error)
self.collision.eq(self.we & collision)
]
# Buffer read and FIFO write
@ -335,7 +335,7 @@ class _KernelCSRs(AutoCSR):
self.o_status = CSRStatus(4)
self.o_underflow_reset = CSR()
self.o_sequence_error_reset = CSR()
self.o_collision_error_reset = CSR()
self.o_collision_reset = CSR()
if data_width:
self.i_data = CSRStatus(data_width)
@ -422,22 +422,22 @@ class RTIO(Module):
underflow = Signal()
sequence_error = Signal()
collision_error = Signal()
collision = Signal()
self.sync.rsys += [
If(selected & self.kcsrs.o_underflow_reset.re,
underflow.eq(0)),
If(selected & self.kcsrs.o_sequence_error_reset.re,
sequence_error.eq(0)),
If(selected & self.kcsrs.o_collision_error_reset.re,
collision_error.eq(0)),
If(selected & self.kcsrs.o_collision_reset.re,
collision.eq(0)),
If(o_manager.underflow, underflow.eq(1)),
If(o_manager.sequence_error, sequence_error.eq(1)),
If(o_manager.collision_error, collision_error.eq(1))
If(o_manager.collision, collision.eq(1))
]
o_statuses.append(Cat(~o_manager.writable,
underflow,
sequence_error,
collision_error))
collision))
if channel.interface.i is not None:
i_manager = _InputManager(channel.interface.i, self.counter,

2
artiq/protocols/analyzer.py
View File

@ -15,6 +15,6 @@ class ExceptionType(Enum):
o_underflow_reset = 0b010000
o_sequence_error_reset = 0b010001
o_collision_error_reset = 0b010010
o_collision_reset = 0b010010
i_overflow_reset = 0b100000

8
artiq/runtime/rtio.c
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@ -33,10 +33,10 @@ static void rtio_process_exceptional_status(
"RTIO sequence error at {0} mu, channel {1}",
timestamp, channel, 0);
}
if(status & RTIO_O_STATUS_COLLISION_ERROR) {
rtio_o_collision_error_reset_write(1);
artiq_raise_from_c("RTIOCollisionError",
"RTIO collision error at {0} mu, channel {1}",
if(status & RTIO_O_STATUS_COLLISION) {
rtio_o_collision_reset_write(1);
artiq_raise_from_c("RTIOCollision",
"RTIO collision at {0} mu, channel {1}",
timestamp, channel, 0);
}
}

2
artiq/runtime/rtio.h
View File

@ -6,7 +6,7 @@
#define RTIO_O_STATUS_FULL 1
#define RTIO_O_STATUS_UNDERFLOW 2
#define RTIO_O_STATUS_SEQUENCE_ERROR 4
#define RTIO_O_STATUS_COLLISION_ERROR 8
#define RTIO_O_STATUS_COLLISION 8
#define RTIO_I_STATUS_EMPTY 1
#define RTIO_I_STATUS_OVERFLOW 2

8
artiq/test/coredevice/test_rtio.py
View File

@ -150,7 +150,7 @@ class SequenceError(EnvExperiment):
self.ttl_out.pulse(25*us)
class CollisionError(EnvExperiment):
class Collision(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("ttl_out_serdes")
@ -220,9 +220,9 @@ class CoredeviceTest(ExperimentCase):
with self.assertRaises(RTIOSequenceError):
self.execute(SequenceError)
def test_collision_error(self):
with self.assertRaises(RTIOCollisionError):
self.execute(CollisionError)
def test_collision(self):
with self.assertRaises(RTIOCollision):
self.execute(Collision)
def test_watchdog(self):
# watchdog only works on the device