Commit Graph

6307 Commits

Author SHA1 Message Date
whitequark
69fa9b38e0 test: actually run test_embedding.AsyncTest. 2017-06-25 05:28:32 +00:00
whitequark
31b52ff1b3 coredevice: do not desync kernel TCP stream on RPCReturnValueError.
And propagate the error upwards instead of trying to squeeze it
through the core device in futility.
2017-06-25 04:47:32 +00:00
whitequark
fdb24ef139 coredevice: truncate overlong exception messages.
If we have a really long one (megabytes) then this may exhaust
the heap of the core device and crash it.
2017-06-25 04:39:08 +00:00
whitequark
1fa8be3835 artiq_devtool: don't loop forever if core device dies. 2017-06-25 04:18:45 +00:00
whitequark
f17a6616b2 runtime: ensure management interface buffer can hold log buffer.
Otherwise we get weird edge cases where the network stack could try
to append to log buffer while management interface is holding
the log buffer and trying to push it out, and it's just no good.

The serialized log buffer at its maximum length is slightly longer
than 32 KiB, so we just allocate the largest possible TCP buffer
to the management interface to keep it simple.
2017-06-24 17:09:28 +00:00
whitequark
d0f72632e1 language: export TBytes and TByteArray. 2017-06-24 17:03:35 +00:00
whitequark
12357d884e runtime: update smoltcp. 2017-06-24 16:55:59 +00:00
07f5e99140 dsp/sat_add: works after previous changes 2017-06-22 18:24:22 +02:00
f78d5a87e9 dsp/test: skip and fix sat_add 2017-06-22 18:01:31 +02:00
47928a2c0d sawg: disable limiter
temporary workaround to permit testing other aspects
2017-06-22 17:31:04 +02:00
cd2ac53bc5 dsp/sat_add: make width mandatory 2017-06-22 17:28:39 +02:00
9b940aa876 dsp/sat_add: spell out logic more 2017-06-22 16:55:13 +02:00
d0cf0f2b87 sawg/limiter: make signed signals explicitly 2017-06-22 13:44:36 +02:00
53be34a25f sawg: clear phase accu in reset 2017-06-22 13:27:49 +02:00
694f8d784c dsp/tools: unittest sat_add 2017-06-22 11:29:56 +02:00
bd1438d28e sawg: wrap limits init values 2017-06-22 10:26:29 +02:00
cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
5f6e665158 test/sawg: patch delay_mu 2017-06-22 10:26:29 +02:00
570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
4b3aad2563 sawg: clean up Config
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
2017-06-22 10:26:29 +02:00
f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
ff0da2c9fc sawg: stage code for y-data exchange on channels 2017-06-22 10:26:29 +02:00
b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
f369cb97f7 sawg/examples: add a bit more slack 2017-06-22 10:26:29 +02:00
05b57f5110 protocols: increase another asyncio line limit (#671) 2017-06-22 09:43:52 +08:00
e3588c9e68 RELEASE_NOTES: 2.4 2017-06-22 00:38:49 +08:00
c2cc29142d drtio: remove misleading comment from device_db 2017-06-21 18:34:53 +08:00
6262969d46 test: relax test_dma_record_time 2017-06-21 18:33:58 +08:00
64ce85445c drtio: add remote converter SPI example (#740) 2017-06-21 17:08:12 +08:00
74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times 2017-06-21 17:01:52 +08:00
66dee9d1ad drtio: send/process I2C and SPI aux packets (#740) 2017-06-21 16:50:51 +08:00
f58f16ccd4 drtioaux: add default timeout 2017-06-21 16:23:11 +08:00
7675dd063b drtioaux: add I2C and SPI packets (#740) 2017-06-21 14:07:16 +08:00
c399bec8da RELEASE_NOTES: pipistrello discontinued by manufacturer 2017-06-20 06:18:34 +02:00
c74de6ae96 phaser: reintroduce test_ad9154_status 2017-06-20 00:49:57 +08:00
8c56a95fa2 spi: add default busno 2017-06-20 00:49:38 +08:00
39ddb66f0f phaser: add AD9154 SPI access driver to example ddb 2017-06-20 00:49:21 +08:00
470bce6214 coredevice: add AD9154 SPI access driver 2017-06-20 00:48:50 +08:00
a6d06824e7 fix indentation 2017-06-20 00:12:11 +08:00
8f2d85fc5b add back ad9154_reg.py 2017-06-19 23:45:32 +08:00
c86029bca2 i2c: expose restart as syscall, add structure for I2C-over-DRTIO 2017-06-19 23:44:51 +08:00
268b7d8aaf typo 2017-06-19 15:42:10 +08:00
09d198c7a1 test: add test for exception on non-existent I2C bus 2017-06-19 15:32:09 +08:00
d08bd58dff versioneer: cut git hashes consistently (#753) 2017-06-19 15:31:48 +08:00
6c6bb67618 libboard: fix compiler warning on not(has_i2c) 2017-06-19 14:57:15 +08:00
5d63489080 i2c,spi: add busno error detection 2017-06-19 14:27:30 +08:00
0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
8399f8893d add kernel access to non-realtime SPI buses (#740) 2017-06-18 12:45:07 +08:00
424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
219dfd8984 rtio: add one register level for rio and rio_phy resets
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00