forked from M-Labs/artiq
dsp/sat_add: spell out logic more
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@ -183,9 +183,9 @@ class Channel(Module, SatAddMixin):
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Cat(b.yi).eq(Cat(hbf[1].o)),
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]
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self.sync += [
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hbf[0].i.eq(self.sat_add(a1.xo[0], a2.xo[0],
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hbf[0].i.eq(self.sat_add((a1.xo[0], a2.xo[0]),
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limits=cfg.limits[1], clipped=cfg.clipped[1])),
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hbf[1].i.eq(self.sat_add(a1.yo[0], a2.yo[0],
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hbf[1].i.eq(self.sat_add((a1.yo[0], a2.yo[0]),
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limits=cfg.limits[1], clipped=cfg.clipped[1])),
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]
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# wire up outputs and q_{i,o} exchange
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@ -199,9 +199,8 @@ class Channel(Module, SatAddMixin):
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o_y.eq(Mux(cfg.iq_en[1], y, 0)),
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]
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self.sync += [
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o.eq(self.sat_add(o_offset, o_x, o_y,
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limits=cfg.limits[0],
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clipped=cfg.clipped[0])),
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o.eq(self.sat_add((o_offset, o_x, o_y),
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limits=cfg.limits[0], clipped=cfg.clipped[0])),
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]
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def connect_y(self, buddy):
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@ -30,34 +30,39 @@ def eqh(a, b):
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class SatAddMixin:
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"""Signed saturating addition mixin"""
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def sat_add(self, *a, limits=None, clipped=None):
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def sat_add(self, a, *, width=None, limits=None, clipped=None):
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a = list(a)
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# assert all(value_bits_sign(ai)[1] for ai in a)
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length = max(len(ai) for ai in a)
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if width is None:
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width = max(value_bits_sign(ai)[0] for ai in a)
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carry = log2_int(len(a), need_pow2=False)
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full = Signal((length + carry, True))
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limited = Signal((length, True))
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full = Signal((width + carry, True))
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limited = Signal((width, True))
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clip = Signal(2)
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sign = Signal()
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if clipped is not None:
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self.comb += clipped.eq(clip)
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self.comb += [
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full.eq(reduce(add, a)),
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sign.eq(full[-1]),
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limited.eq(full)
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]
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if limits is None:
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sign = Signal()
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self.comb += [
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sign.eq(full[-1]),
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If(full[-1-carry:] == Replicate(sign, carry + 1),
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clip.eq(0),
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limited.eq(full),
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).Else(
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If(full[-1-carry:] != Replicate(sign, carry + 1),
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clip.eq(Cat(sign, ~sign)),
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limited.eq(Cat(Replicate(~sign, length - 1), sign)),
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limited.eq(Cat(Replicate(~sign, width - 1), sign)),
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)
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]
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else:
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self.comb += [
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clip.eq(Cat(full < limits[0], full > limits[1])),
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limited.eq(Array([full, limits[0], limits[1], 0])[clip]),
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If(full < limits[0],
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clip.eq(0b01),
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limited.eq(limits[0])
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),
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If(full > limits[1],
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clip.eq(0b10),
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limited.eq(limits[1]),
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)
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]
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return limited
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