forked from M-Labs/artiq
dsp/sat_add: make width mandatory
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9b940aa876
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cd2ac53bc5
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@ -184,8 +184,10 @@ class Channel(Module, SatAddMixin):
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]
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self.sync += [
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hbf[0].i.eq(self.sat_add((a1.xo[0], a2.xo[0]),
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width=len(hbf[0].i),
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limits=cfg.limits[1], clipped=cfg.clipped[1])),
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hbf[1].i.eq(self.sat_add((a1.yo[0], a2.yo[0]),
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width=len(hbf[1].i),
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limits=cfg.limits[1], clipped=cfg.clipped[1])),
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]
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# wire up outputs and q_{i,o} exchange
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@ -200,6 +202,7 @@ class Channel(Module, SatAddMixin):
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]
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self.sync += [
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o.eq(self.sat_add((o_offset, o_x, o_y),
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width=len(o),
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limits=cfg.limits[0], clipped=cfg.clipped[0])),
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]
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@ -30,14 +30,15 @@ def eqh(a, b):
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class SatAddMixin:
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"""Signed saturating addition mixin"""
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def sat_add(self, a, *, width=None, limits=None, clipped=None):
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def sat_add(self, a, width, limits=None, clipped=None):
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a = list(a)
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# assert all(value_bits_sign(ai)[1] for ai in a)
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if width is None:
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width = max(value_bits_sign(ai)[0] for ai in a)
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max_width = max(value_bits_sign(ai)[0] for ai in a)
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carry = log2_int(len(a), need_pow2=False)
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full = Signal((width + carry, True))
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full = Signal((max_width + carry, True))
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limited = Signal((width, True))
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carry = len(full) - width
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assert carry >= 0
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clip = Signal(2)
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sign = Signal()
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if clipped is not None:
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