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a8545fc1f7
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targets/kc705: set up user_sma_gpio_n like other TTLs
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2016-02-22 22:35:15 +08:00 |
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4946a53456
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Revert "targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance"
This reverts commit 04b0db1a91.
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2016-02-22 17:52:40 +08:00 |
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d1119d7747
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artiq_dir: move out of tools to unlink dependencies
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2016-01-25 18:15:50 -07:00 |
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18f0ee814d
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gateware: add QC1 docstring
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2016-01-20 21:27:22 -05:00 |
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db8ba8d6c1
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gateware: add clock target from David
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2016-01-20 21:23:49 -05:00 |
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b3ba97e431
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gateware: clean up and integrate QC2 modifications from Daniel
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2016-01-20 21:17:19 -05:00 |
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cb5fd08713
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targets/kc705: fix e664fe3
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2016-01-20 09:38:44 -05:00 |
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e664fe38b0
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targets/kc705: fix DDS_RTIO_CLK_RATIO for AD9914. Closes #238
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2016-01-20 09:18:50 -05:00 |
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87dd09a71c
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gateware: compress bitstreams
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2016-01-06 15:40:28 -07:00 |
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04b0db1a91
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targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance
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2015-12-29 17:00:57 +08:00 |
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ba6c527819
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gateware/targets: add RTIO log channels
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2015-12-26 22:44:01 +08:00 |
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4def561710
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targets: integrate RTIO analyzer
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2015-12-16 17:36:52 +08:00 |
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bf29e8ddc6
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kc705: make config[] usage consistent
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2015-12-15 12:14:30 -07:00 |
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7886827b80
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CSRConstant: also port DDS constants
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2015-12-04 18:27:59 +08:00 |
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5db1f9794e
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top.add_constant() -> top.config[] (CSRConstant)
This is to be synchronized with the corresponding change in misoc.
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2015-12-04 18:27:54 +08:00 |
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ae99af27ee
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runtime,gateware: use new misoc identifier
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2015-11-10 22:44:38 +08:00 |
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whitequark
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51f04f6311
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Explicitly use the python3.5 binary everywhere.
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2015-11-07 13:39:39 +03:00 |
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ad5a32fb6e
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targets/kc705: remove unneeded argument on qc2
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2015-11-04 20:09:37 +08:00 |
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e26147b2ac
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gateware,runtime: use new migen/misoc
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2015-11-04 00:35:03 +08:00 |
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