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top.add_constant() -> top.config[] (CSRConstant) 

This is to be synchronized with the corresponding change in misoc.
This commit is contained in:
Robert Jördens 2015-12-04 00:57:39 -07:00 committed by Sebastien Bourdeauducq
parent 0d90d88eff
commit 5db1f9794e
12 changed files with 56 additions and 56 deletions
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16
artiq/gateware/targets/kc705.py
View File

@ -111,9 +111,9 @@ class _NIST_QCx(MiniSoC, AMPSoC):
def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
assert self.rtio.fine_ts_width <= 3
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
@ -167,14 +167,14 @@ class NIST_QC1(_NIST_QCx):
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("ttl", 15))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
self.add_constant("DDS_CHANNEL_COUNT", 8)
self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
self.config["DDS_CHANNEL_COUNT"] = 8
self.add_constant("DDS_AD9858")
phy = dds.AD9858(platform.request("dds"), 8)
self.submodules += phy
@ -211,14 +211,14 @@ class NIST_QC2(_NIST_QCx):
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("ttl", 14))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
self.add_constant("DDS_CHANNEL_COUNT", 11)
self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
self.config["DDS_CHANNEL_COUNT"] = 11
self.add_constant("DDS_AD9914")
self.add_constant("DDS_ONEHOT_SEL")
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)

10
artiq/gateware/targets/pipistrello.py
View File

@ -173,14 +173,14 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
self.add_constant("RTIO_REGULAR_TTL_COUNT", len(rtio_channels))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("ttl", 15))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
self.add_constant("DDS_CHANNEL_COUNT", 8)
self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
self.config["DDS_CHANNEL_COUNT"] = 8
self.add_constant("DDS_AD9858")
dds_pins = platform.request("dds")
self.comb += dds_pins.p.eq(0)
@ -192,8 +192,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
# RTIO core
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
# CPU connections

4
artiq/runtime/bridge.c
View File

@ -5,11 +5,11 @@
#include "dds.h"
#include "bridge.h"
#define TIME_BUFFER (8000 << RTIO_FINE_TS_WIDTH)
#define TIME_BUFFER (8000 << CONFIG_RTIO_FINE_TS_WIDTH)
static void dds_write(int addr, int data)
{
rtio_chan_sel_write(RTIO_DDS_CHANNEL);
rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
rtio_o_address_write(addr);
rtio_o_data_write(data);
rtio_o_timestamp_write(rtio_get_counter() + TIME_BUFFER);

4
artiq/runtime/clock.c
View File

@ -20,7 +20,7 @@ long long int clock_get_ms(void)
timer0_update_value_write(1);
clock_sys = 0x7fffffffffffffffLL - timer0_value_read();
clock_ms = clock_sys/(SYSTEM_CLOCK_FREQUENCY/1000);
clock_ms = clock_sys/(CONFIG_CLOCK_FREQUENCY/1000);
return clock_ms;
}
@ -29,7 +29,7 @@ void busywait_us(long long int us)
long long int threshold;
timer0_update_value_write(1);
threshold = timer0_value_read() - us*SYSTEM_CLOCK_FREQUENCY/1000000LL;
threshold = timer0_value_read() - us*CONFIG_CLOCK_FREQUENCY/1000000LL;
while(timer0_value_read() > threshold)
timer0_update_value_write(1);
}

22
artiq/runtime/dds.c
View File

@ -6,7 +6,7 @@
#include "log.h"
#include "dds.h"
#define DURATION_WRITE (5 << RTIO_FINE_TS_WIDTH)
#define DURATION_WRITE (5 << CONFIG_RTIO_FINE_TS_WIDTH)
#if defined DDS_AD9858
/* Assume 8-bit bus */
@ -16,7 +16,7 @@
#elif defined DDS_AD9914
/* Assume 16-bit bus */
/* DAC calibration takes max. 1ms as per datasheet */
#define DURATION_DAC_CAL (147000 << RTIO_FINE_TS_WIDTH)
#define DURATION_DAC_CAL (147000 << CONFIG_RTIO_FINE_TS_WIDTH)
/* not counting final FUD */
#define DURATION_INIT (8*DURATION_WRITE + DURATION_DAC_CAL)
#define DURATION_PROGRAM (6*DURATION_WRITE) /* not counting FUD */
@ -29,7 +29,7 @@
rtio_o_address_write(addr); \
rtio_o_data_write(data); \
rtio_o_timestamp_write(now); \
rtio_write_and_process_status(now, RTIO_DDS_CHANNEL); \
rtio_write_and_process_status(now, CONFIG_RTIO_DDS_CHANNEL); \
now += DURATION_WRITE; \
} while(0)
@ -37,7 +37,7 @@ void dds_init(long long int timestamp, int channel)
{
long long int now;
rtio_chan_sel_write(RTIO_DDS_CHANNEL);
rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
now = timestamp - DURATION_INIT;
@ -87,14 +87,14 @@ void dds_init(long long int timestamp, int channel)
/* Compensation to keep phase continuity when switching from absolute or tracking
* to continuous phase mode. */
static unsigned int continuous_phase_comp[DDS_CHANNEL_COUNT];
static unsigned int continuous_phase_comp[CONFIG_DDS_CHANNEL_COUNT];
static void dds_set_one(long long int now, long long int ref_time, unsigned int channel,
unsigned int ftw, unsigned int pow, int phase_mode, unsigned int amplitude)
{
unsigned int channel_enc;
if(channel >= DDS_CHANNEL_COUNT) {
if(channel >= CONFIG_DDS_CHANNEL_COUNT) {
log("Attempted to set invalid DDS channel");
return;
}
@ -118,7 +118,7 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
#endif
/* We need the RTIO fine timestamp clock to be phase-locked
* to DDS SYSCLK, and divided by an integer DDS_RTIO_CLK_RATIO.
* to DDS SYSCLK, and divided by an integer CONFIG_DDS_RTIO_CLK_RATIO.
*/
if(phase_mode == PHASE_MODE_CONTINUOUS) {
/* Do not clear phase accumulator on FUD */
@ -142,9 +142,9 @@ static void dds_set_one(long long int now, long long int ref_time, unsigned int
DDS_WRITE(DDS_CFR1L, 0x2108);
#endif
fud_time = now + 2*DURATION_WRITE;
pow -= (ref_time - fud_time)*DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
pow -= (ref_time - fud_time)*CONFIG_DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
if(phase_mode == PHASE_MODE_TRACKING)
pow += ref_time*DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
pow += ref_time*CONFIG_DDS_RTIO_CLK_RATIO*ftw >> (32-DDS_POW_WIDTH);
continuous_phase_comp[channel] = pow;
}
@ -190,7 +190,7 @@ void dds_batch_exit(void)
if(!batch_mode)
artiq_raise_from_c("DDSBatchError", "DDS batch error", 0, 0, 0);
rtio_chan_sel_write(RTIO_DDS_CHANNEL);
rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
/* + FUD time */
now = batch_ref_time - batch_count*(DURATION_PROGRAM + DURATION_WRITE);
for(i=0;i<batch_count;i++) {
@ -216,7 +216,7 @@ void dds_set(long long int timestamp, int channel,
batch[batch_count].amplitude = amplitude;
batch_count++;
} else {
rtio_chan_sel_write(RTIO_DDS_CHANNEL);
rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
dds_set_one(timestamp - DURATION_PROGRAM, timestamp, channel, ftw, pow, phase_mode,
amplitude);
}

6
artiq/runtime/flash_storage.c
View File

@ -12,10 +12,10 @@
#include "log.h"
#include "flash_storage.h"
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
#define STORAGE_ADDRESS ((char *)(FLASH_BOOT_ADDRESS + 256*1024))
#define STORAGE_SIZE SPIFLASH_SECTOR_SIZE
#define STORAGE_SIZE CONFIG_SPIFLASH_SECTOR_SIZE
#define END_MARKER (0xFFFFFFFF)
#define min(a, b) (a>b?b:a)
@ -302,4 +302,4 @@ void fs_remove(const char *key)
fs_write(key, NULL, 0);
}
#endif /* CSR_SPIFLASH_BASE && SPIFLASH_PAGE_SIZE */
#endif /* CSR_SPIFLASH_BASE && CONFIG_SPIFLASH_PAGE_SIZE */

2
artiq/runtime/kloader.c
View File

@ -90,7 +90,7 @@ void kloader_start_kernel()
static int kloader_start_flash_kernel(char *key)
{
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
char buffer[32*1024];
unsigned int length, remain;

2
artiq/runtime/ksupport.c
View File

@ -268,7 +268,7 @@ long long int now_init(void)
if(now < 0) {
rtio_init();
now = rtio_get_counter() + (272000 << RTIO_FINE_TS_WIDTH);
now = rtio_get_counter() + (272000 << CONFIG_RTIO_FINE_TS_WIDTH);
}
return now;

8
artiq/runtime/main.c
View File

@ -64,14 +64,14 @@ static int hex2nib(int c)
static void init_macadr(void)
{
static const unsigned char default_macadr[6] = {0x10, 0xe2, 0xd5, 0x32, 0x50, 0x00};
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
char b[32];
char fs_macadr[6];
int i, r, s;
#endif
memcpy(macadr, default_macadr, 6);
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
r = fs_read("mac", b, sizeof(b) - 1, NULL);
if(r <= 0)
return;
@ -93,12 +93,12 @@ static void init_macadr(void)
static void fsip_or_default(struct ip4_addr *d, char *key, int i1, int i2, int i3, int i4)
{
int r;
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
char cp[32];
#endif
IP4_ADDR(d, i1, i2, i3, i4);
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
r = fs_read(key, cp, sizeof(cp) - 1, NULL);
if(r <= 0)
return;

8
artiq/runtime/moninj.c
View File

@ -39,7 +39,7 @@ struct monitor_reply {
long long int ttl_levels;
long long int ttl_oes;
long long int ttl_overrides;
unsigned int dds_ftws[DDS_CHANNEL_COUNT];
unsigned int dds_ftws[CONFIG_DDS_CHANNEL_COUNT];
};
static void moninj_monitor(const ip_addr_t *addr, u16_t port)
@ -51,7 +51,7 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
reply.ttl_levels = 0;
reply.ttl_oes = 0;
reply.ttl_overrides = 0;
for(i=0;i<RTIO_REGULAR_TTL_COUNT;i++) {
for(i=0;i<CONFIG_RTIO_REGULAR_TTL_COUNT;i++) {
rtio_moninj_mon_chan_sel_write(i);
rtio_moninj_mon_probe_sel_write(0);
rtio_moninj_mon_value_update_write(1);
@ -67,8 +67,8 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
reply.ttl_overrides |= 1LL << i;
}
rtio_moninj_mon_chan_sel_write(RTIO_DDS_CHANNEL);
for(i=0;i<DDS_CHANNEL_COUNT;i++) {
rtio_moninj_mon_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
for(i=0;i<CONFIG_DDS_CHANNEL_COUNT;i++) {
rtio_moninj_mon_probe_sel_write(i);
rtio_moninj_mon_value_update_write(1);
reply.dds_ftws[i] = rtio_moninj_mon_value_read();

4
artiq/runtime/session.c
View File

@ -432,7 +432,7 @@ static int process_input(void)
break;
case REMOTEMSG_TYPE_FLASH_READ_REQUEST: {
#if SPIFLASH_SECTOR_SIZE - 4 > BUFFER_OUT_SIZE - 9
#if CONFIG_SPIFLASH_SECTOR_SIZE - 4 > BUFFER_OUT_SIZE - 9
#error Output buffer cannot hold the flash storage data
#endif
const char *key = in_packet_string();
@ -447,7 +447,7 @@ static int process_input(void)
}
case REMOTEMSG_TYPE_FLASH_WRITE_REQUEST: {
#if SPIFLASH_SECTOR_SIZE - 4 > BUFFER_IN_SIZE - 9
#if CONFIG_SPIFLASH_SECTOR_SIZE - 4 > BUFFER_IN_SIZE - 9
#error Input buffer cannot hold the flash storage data
#endif
const char *key, *value;

26
artiq/runtime/test_mode.c
View File

@ -330,15 +330,15 @@ static void ddstest(char *n, char *channel)
do_ddstest_one(channel2);
} else {
for(i=0;i<n2;i++)
for(j=0;j<DDS_CHANNEL_COUNT;j++)
for(j=0;j<CONFIG_DDS_CHANNEL_COUNT;j++)
do_ddstest_one(j);
}
}
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
static void fsread(char *key)
{
char readbuf[SPIFLASH_SECTOR_SIZE];
char readbuf[CONFIG_SPIFLASH_SECTOR_SIZE];
int r;
r = fs_read(key, readbuf, sizeof(readbuf)-1, NULL);
@ -361,13 +361,13 @@ static void fsfull(void)
char value[4096];
memset(value, '@', sizeof(value));
for(i = 0; i < SPIFLASH_SECTOR_SIZE/sizeof(value); i++)
for(i = 0; i < CONFIG_SPIFLASH_SECTOR_SIZE/sizeof(value); i++)
fs_write("plip", value, sizeof(value));
}
static void check_read(char *key, char *expected, unsigned int length, unsigned int testnum)
{
char readbuf[SPIFLASH_SECTOR_SIZE];
char readbuf[CONFIG_SPIFLASH_SECTOR_SIZE];
unsigned int remain, readlength;
memset(readbuf, '\0', sizeof(readbuf));
@ -417,7 +417,7 @@ static inline void test_sector_is_full(void)
fs_erase();
memset(value, '@', sizeof(value));
for(c = 1; c <= SPIFLASH_SECTOR_SIZE/sizeof(value); c++) {
for(c = 1; c <= CONFIG_SPIFLASH_SECTOR_SIZE/sizeof(value); c++) {
key[0] = c;
check_write(fs_write(key, value, sizeof(value) - 6));
}
@ -427,7 +427,7 @@ static inline void test_sector_is_full(void)
static void test_one_big_record(int testnum)
{
char value[SPIFLASH_SECTOR_SIZE];
char value[CONFIG_SPIFLASH_SECTOR_SIZE];
memset(value, '@', sizeof(value));
fs_erase();
@ -450,12 +450,12 @@ static void test_one_big_record(int testnum)
static void test_flush_duplicate_rollback(int testnum)
{
char value[SPIFLASH_SECTOR_SIZE];
char value[CONFIG_SPIFLASH_SECTOR_SIZE];
memset(value, '@', sizeof(value));
fs_erase();
/* This makes the flash storage full with one big record */
check_write(fs_write("a", value, SPIFLASH_SECTOR_SIZE - 6));
check_write(fs_write("a", value, CONFIG_SPIFLASH_SECTOR_SIZE - 6));
/* This should trigger the try_to_flush_duplicate code which
* at first will not keep the old "a" record value because we are
* overwriting it. But then it should roll back to the old value
@ -465,12 +465,12 @@ static void test_flush_duplicate_rollback(int testnum)
check_write(!fs_write("a", value, sizeof(value)));
/* check we still have the old record value */
value[0] = '@';
check_read("a", value, SPIFLASH_SECTOR_SIZE - 6, testnum);
check_read("a", value, CONFIG_SPIFLASH_SECTOR_SIZE - 6, testnum);
}
static void test_too_big_fails(int testnum)
{
char value[SPIFLASH_SECTOR_SIZE];
char value[CONFIG_SPIFLASH_SECTOR_SIZE];
memset(value, '@', sizeof(value));
fs_erase();
@ -551,7 +551,7 @@ static void help(void)
puts("ddsftw <n> <d> - write FTW");
puts("ddstest <n> <c> - perform test sequence on DDS");
puts("leds <n> - set LEDs");
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
puts("fserase - erase flash storage");
puts("fswrite <k> <v> - write to flash storage");
puts("fsread <k> - read flash storage");
@ -633,7 +633,7 @@ static void do_command(char *c)
else if(strcmp(token, "ddsftw") == 0) ddsftw(get_token(&c), get_token(&c));
else if(strcmp(token, "ddstest") == 0) ddstest(get_token(&c), get_token(&c));
#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
#if (defined CSR_SPIFLASH_BASE && defined CONFIG_SPIFLASH_PAGE_SIZE)
else if(strcmp(token, "fserase") == 0) fs_erase();
else if(strcmp(token, "fswrite") == 0) fswrite(get_token(&c), c, strlen(c));
else if(strcmp(token, "fsread") == 0) fsread(get_token(&c));