forked from M-Labs/artiq
gateware/targets: add RTIO log channels
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080752092c
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@ -185,6 +185,10 @@ class NIST_QC1(_NIST_QCx):
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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@ -230,6 +234,10 @@ class NIST_QC2(_NIST_QCx):
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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@ -190,6 +190,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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ofifo_depth=512,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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# RTIO core
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
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