forked from M-Labs/artiq
kc705: fix gtx clock path durnig init
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8f7d138dbd
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ec2b86b08d
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@ -273,7 +273,8 @@ class _MasterBase(MiniSoC, AMPSoC):
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txout_buf = Signal()
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
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self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
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@ -440,7 +441,8 @@ class _SatelliteBase(BaseSoC, AMPSoC):
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txout_buf = Signal()
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self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
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self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
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self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
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