From ec2b86b08d497a41e75c228385b754c6f3a4a8bf Mon Sep 17 00:00:00 2001 From: linuswck Date: Tue, 7 Nov 2023 12:04:24 +0800 Subject: [PATCH] kc705: fix gtx clock path durnig init --- artiq/gateware/targets/kc705.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 1c62476e5..b3b5a4af7 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -273,7 +273,8 @@ class _MasterBase(MiniSoC, AMPSoC): txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) - self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done) + self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), @@ -440,7 +441,8 @@ class _SatelliteBase(BaseSoC, AMPSoC): txout_buf = Signal() self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf) - self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done) + self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done) + self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap") self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),