forked from M-Labs/artiq
runtime: add riscv
This commit is contained in:
parent
ecedec577c
commit
e99061b013
|
@ -28,6 +28,7 @@ logger_artiq = { path = "../liblogger_artiq" }
|
|||
board_artiq = { path = "../libboard_artiq" }
|
||||
proto_artiq = { path = "../libproto_artiq", features = ["log", "alloc"] }
|
||||
smoltcp = { version = "0.6.0", default-features = false, features = ["rust-1_28", "alloc", "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp"] }
|
||||
riscv = { version = "0.6.0", features = ["inline-asm"] }
|
||||
|
||||
[dependencies.fringe]
|
||||
git = "https://github.com/m-labs/libfringe"
|
||||
|
|
|
@ -25,6 +25,7 @@ extern crate board_misoc;
|
|||
extern crate board_artiq;
|
||||
extern crate logger_artiq;
|
||||
extern crate proto_artiq;
|
||||
extern crate riscv;
|
||||
|
||||
use core::cell::RefCell;
|
||||
use core::convert::TryFrom;
|
||||
|
@ -41,6 +42,8 @@ use proto_artiq::{mgmt_proto, moninj_proto, rpc_proto, session_proto, kernel_pro
|
|||
#[cfg(has_rtio_analyzer)]
|
||||
use proto_artiq::analyzer_proto;
|
||||
|
||||
use riscv::register::{mcause, mepc};
|
||||
|
||||
mod rtio_clocking;
|
||||
mod rtio_mgt;
|
||||
|
||||
|
|
Loading…
Reference in New Issue