From d780faf4ac324311b5c4b00ad8f469bbb4fa77c4 Mon Sep 17 00:00:00 2001 From: hartytp Date: Wed, 7 Oct 2020 10:11:25 +0100 Subject: [PATCH] wrpll.si549: initialize the clock divider to a sensible value --- artiq/gateware/drtio/wrpll/si549.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/wrpll/si549.py b/artiq/gateware/drtio/wrpll/si549.py index 6f840854c..46ce0c138 100644 --- a/artiq/gateware/drtio/wrpll/si549.py +++ b/artiq/gateware/drtio/wrpll/si549.py @@ -255,7 +255,7 @@ class Si549(Module, AutoCSR): self.gpio_out = CSRStorage(2) self.gpio_oe = CSRStorage(2) - self.i2c_divider = CSRStorage(16, reset=2500) + self.i2c_divider = CSRStorage(16, reset=75) self.i2c_address = CSRStorage(7) self.errors = CSR(2)