forked from M-Labs/artiq
rv32: rm irq & vexriscv-rust
Signed-off-by: occheung <dc@m-labs.hk>
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@ -17,7 +17,6 @@ byteorder = { version = "1.0", default-features = false }
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log = { version = "0.4", default-features = false, optional = true }
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smoltcp = { version = "0.6.0", default-features = false, optional = true }
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riscv = { version = "0.6.0", features = ["inline-asm"] }
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vexriscv = { git = "https://github.com/occheung/vexriscv-rust.git", features = ["inline-asm"] }
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[features]
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uart_console = []
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@ -18,9 +18,6 @@ mod arch;
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#[cfg(target_arch = "riscv32")]
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extern crate riscv;
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#[cfg(target_arch = "riscv32")]
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extern crate vexriscv;
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pub use arch::*;
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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@ -1,46 +0,0 @@
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use core::{convert::TryFrom};
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use riscv::register::mstatus;
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use vexriscv::register::{vmim, vmip};
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#[inline]
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pub fn get_ie() -> bool {
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mstatus::read().mie()
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}
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#[inline]
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pub fn set_ie(ie: bool) {
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unsafe {
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if ie {
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mstatus::set_mie()
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} else {
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mstatus::clear_mie()
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}
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}
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}
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#[inline]
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pub fn get_mask() -> u32 {
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u32::try_from(vmim::read()).unwrap()
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}
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#[inline]
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pub fn set_mask(mask: u32) {
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vmim::write(usize::try_from(mask).unwrap())
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}
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#[inline]
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pub fn pending_mask() -> u32 {
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u32::try_from(vmip::read()).unwrap()
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}
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pub fn enable(irq: u32) {
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set_mask(get_mask() | (1 << irq))
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}
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pub fn disable(irq: u32) {
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set_mask(get_mask() & !(1 << irq))
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}
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pub fn is_pending(irq: u32) -> bool {
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get_mask() & (1 << irq) != 0
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}
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@ -1,3 +1,2 @@
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pub mod irq;
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pub mod cache;
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pub mod boot;
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