diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py
index 6a1e6615e..0a1302191 100644
--- a/artiq/gateware/rtio/analyzer.py
+++ b/artiq/gateware/rtio/analyzer.py
@@ -175,6 +175,7 @@ class DMAWriter(Module, AutoCSR):
         # # #
 
         self.comb += [
+            membus.cyc.eq(self.sink.stb),
             membus.stb.eq(self.sink.stb),
             self.sink.ack.eq(membus.ack),
             membus.we.eq(1),