From b5ec979db3a527451c0c68d128f1ab0b328df038 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 15 Mar 2016 19:46:12 +0800
Subject: [PATCH] analyzer: drive wishbone cyc signal

---
 artiq/gateware/rtio/analyzer.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py
index 6a1e6615e..0a1302191 100644
--- a/artiq/gateware/rtio/analyzer.py
+++ b/artiq/gateware/rtio/analyzer.py
@@ -175,6 +175,7 @@ class DMAWriter(Module, AutoCSR):
         # # #
 
         self.comb += [
+            membus.cyc.eq(self.sink.stb),
             membus.stb.eq(self.sink.stb),
             self.sink.ack.eq(membus.ack),
             membus.we.eq(1),