forked from M-Labs/artiq
kernel: flush cache before mod_init
This could be necessary as redirecting instructions from D$ directly to I$ as it seems. Related: https://github.com/SpinalHDL/VexRiscv/issues/137
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@ -498,6 +498,9 @@ pub unsafe fn main() {
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ptr::write_bytes(__bss_start as *mut u8, 0, (_end - __bss_start) as usize);
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ptr::write_bytes(__bss_start as *mut u8, 0, (_end - __bss_start) as usize);
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board_misoc::cache::flush_cpu_dcache();
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board_misoc::cache::flush_cpu_icache();
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(mem::transmute::<u32, fn()>(__modinit__))();
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(mem::transmute::<u32, fn()>(__modinit__))();
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if let Some(typeinfo) = typeinfo {
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if let Some(typeinfo) = typeinfo {
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