From b091d8cb660bcfb48cb7b5d1672fed12ef330cbd Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Fri, 10 Sep 2021 11:07:51 +0800
Subject: [PATCH] kernel: flush cache before mod_init

This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
---
 artiq/firmware/ksupport/lib.rs | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/artiq/firmware/ksupport/lib.rs b/artiq/firmware/ksupport/lib.rs
index 73bc3d284..aaedbd018 100644
--- a/artiq/firmware/ksupport/lib.rs
+++ b/artiq/firmware/ksupport/lib.rs
@@ -498,6 +498,9 @@ pub unsafe fn main() {
 
     ptr::write_bytes(__bss_start as *mut u8, 0, (_end - __bss_start) as usize);
 
+    board_misoc::cache::flush_cpu_dcache();
+    board_misoc::cache::flush_cpu_icache();
+
     (mem::transmute::<u32, fn()>(__modinit__))();
 
     if let Some(typeinfo) = typeinfo {