srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

gateware/suservo: write to profile 7 

Fixes #1817.
This commit is contained in:
occheung 2022-01-07 16:36:28 +08:00
parent bbac477092
commit 9d493028e5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/suservo/dds_ser.py
View File

@ -26,7 +26,7 @@ class DDS(spi.SPISimple):
self.profile = [Signal(32 + 16 + 16, reset_less=True) self.profile = [Signal(32 + 16 + 16, reset_less=True)
for i in range(params.channels)] for i in range(params.channels)]
cmd = Signal(8, reset=0x0e) # write to single tone profile 0 cmd = Signal(8, reset=0x15) # write to single tone profile 7
assert params.width == len(cmd) + len(self.profile[0]) assert params.width == len(cmd) + len(self.profile[0])
self.sync += [ self.sync += [