From 9d493028e5c6f70e9c10bbf7571bbdea251f2415 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Fri, 7 Jan 2022 16:36:28 +0800
Subject: [PATCH] gateware/suservo: write to profile 7

Fixes #1817.
---
 artiq/gateware/suservo/dds_ser.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/suservo/dds_ser.py b/artiq/gateware/suservo/dds_ser.py
index 8df30e9fe..7a53f352e 100644
--- a/artiq/gateware/suservo/dds_ser.py
+++ b/artiq/gateware/suservo/dds_ser.py
@@ -26,7 +26,7 @@ class DDS(spi.SPISimple):
 
         self.profile = [Signal(32 + 16 + 16, reset_less=True)
                 for i in range(params.channels)]
-        cmd = Signal(8, reset=0x0e)  # write to single tone profile 0
+        cmd = Signal(8, reset=0x15)  # write to single tone profile 7
         assert params.width == len(cmd) + len(self.profile[0])
 
         self.sync += [