forked from M-Labs/artiq
drtio: squelch frame signals until link layer ready
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@ -232,11 +232,23 @@ class LinkLayer(Module):
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# in rtio_rx clock domain
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self.rx_aux_stb = rx.aux_stb
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self.rx_aux_frame = rx.aux_frame
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self.rx_aux_frame = Signal()
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self.rx_aux_data = rx.aux_data
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self.rx_rt_frame = rx.rt_frame
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self.rx_rt_frame = Signal()
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self.rx_rt_data = rx.rt_data
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ready_r = Signal()
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ready_rx = Signal()
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self.sync.rtio += ready_r.eq(self.ready)
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self.specials += [
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NoRetiming(ready_r),
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MultiReg(ready_r, ready_rx, "rtio_rx")
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]
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self.comb += [
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self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
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self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
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]
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# # #
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fsm = ClockDomainsRenamer("rtio")(
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@ -173,6 +173,9 @@ class TestFullStack(unittest.TestCase):
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self.assertEqual(err_present, 0)
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def test():
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while not (yield dut.master.link_layer.ready):
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yield
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yield from test_init()
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yield from test_underflow()
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yield from test_pulses()
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