From 95def81c03e8bb72f9276f04dfe4796add455a93 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 29 Oct 2016 17:05:30 +0800
Subject: [PATCH] drtio: squelch frame signals until link layer ready

---
 artiq/gateware/drtio/link_layer.py           | 16 ++++++++++++++--
 artiq/test/gateware/drtio/test_full_stack.py |  3 +++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/drtio/link_layer.py b/artiq/gateware/drtio/link_layer.py
index bf5f771ec..a1946e228 100644
--- a/artiq/gateware/drtio/link_layer.py
+++ b/artiq/gateware/drtio/link_layer.py
@@ -232,11 +232,23 @@ class LinkLayer(Module):
 
         # in rtio_rx clock domain
         self.rx_aux_stb = rx.aux_stb
-        self.rx_aux_frame = rx.aux_frame
+        self.rx_aux_frame = Signal()
         self.rx_aux_data = rx.aux_data
-        self.rx_rt_frame = rx.rt_frame
+        self.rx_rt_frame = Signal()
         self.rx_rt_data = rx.rt_data
 
+        ready_r = Signal()
+        ready_rx = Signal()
+        self.sync.rtio += ready_r.eq(self.ready)
+        self.specials += [
+            NoRetiming(ready_r),
+            MultiReg(ready_r, ready_rx, "rtio_rx")
+        ]
+        self.comb += [
+            self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
+            self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
+        ]
+
         # # #
 
         fsm = ClockDomainsRenamer("rtio")(
diff --git a/artiq/test/gateware/drtio/test_full_stack.py b/artiq/test/gateware/drtio/test_full_stack.py
index e121aa716..22d1eb068 100644
--- a/artiq/test/gateware/drtio/test_full_stack.py
+++ b/artiq/test/gateware/drtio/test_full_stack.py
@@ -173,6 +173,9 @@ class TestFullStack(unittest.TestCase):
             self.assertEqual(err_present, 0)
 
         def test():
+            while not (yield dut.master.link_layer.ready):
+                yield
+
             yield from test_init()
             yield from test_underflow()
             yield from test_pulses()