forked from M-Labs/artiq
Add ARTIQ_DUMP_ASSEMBLY.
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8b7d38d203
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@ -1,4 +1,4 @@
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import tempfile, subprocess
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import os, sys, tempfile, subprocess
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from llvmlite_artiq import ir as ll, binding as llvm
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from llvmlite_artiq import ir as ll, binding as llvm
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llvm.initialize()
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llvm.initialize()
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@ -56,10 +56,20 @@ class Target:
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def compile(self, module):
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def compile(self, module):
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"""Compile the module to a relocatable object for this target."""
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"""Compile the module to a relocatable object for this target."""
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if os.getenv('ARTIQ_DUMP_IR'):
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print("====== ARTIQ IR DUMP ======", file=sys.stderr)
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for function in module.artiq_ir:
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print(function, file=sys.stderr)
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llmod = module.build_llvm_ir(self)
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llmod = module.build_llvm_ir(self)
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llparsedmod = llvm.parse_assembly(str(llmod))
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llparsedmod = llvm.parse_assembly(str(llmod))
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llparsedmod.verify()
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llparsedmod.verify()
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if os.getenv('ARTIQ_DUMP_LLVM'):
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print("====== LLVM IR DUMP ======", file=sys.stderr)
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print(str(llparsedmod), file=sys.stderr)
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llpassmgrbuilder = llvm.create_pass_manager_builder()
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llpassmgrbuilder = llvm.create_pass_manager_builder()
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llpassmgrbuilder.opt_level = 2 # -O2
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llpassmgrbuilder.opt_level = 2 # -O2
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llpassmgrbuilder.size_level = 1 # -Os
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llpassmgrbuilder.size_level = 1 # -Os
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@ -68,10 +78,19 @@ class Target:
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llpassmgrbuilder.populate(llpassmgr)
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llpassmgrbuilder.populate(llpassmgr)
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llpassmgr.run(llparsedmod)
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llpassmgr.run(llparsedmod)
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if os.getenv('ARTIQ_DUMP_LLVM'):
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print("====== LLVM IR DUMP (OPTIMIZED) ======", file=sys.stderr)
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print(str(llparsedmod), file=sys.stderr)
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lltarget = llvm.Target.from_triple(self.triple)
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lltarget = llvm.Target.from_triple(self.triple)
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llmachine = lltarget.create_target_machine(
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llmachine = lltarget.create_target_machine(
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features=",".join(self.features),
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features=",".join(self.features),
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reloc="pic", codemodel="default")
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reloc="pic", codemodel="default")
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if os.getenv('ARTIQ_DUMP_ASSEMBLY'):
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print("====== ASSEMBLY DUMP ======", file=sys.stderr)
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print(llmachine.emit_assembly(llparsedmod), file=sys.stderr)
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return llmachine.emit_object(llparsedmod)
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return llmachine.emit_object(llparsedmod)
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def compile_and_link(self, modules):
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def compile_and_link(self, modules):
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@ -1,4 +1,4 @@
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import os, sys, tempfile
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import sys, tempfile
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from pythonparser import diagnostic
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from pythonparser import diagnostic
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@ -35,15 +35,6 @@ class Core:
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module = Module(stitcher)
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module = Module(stitcher)
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target = OR1KTarget()
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target = OR1KTarget()
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if os.getenv('ARTIQ_DUMP_IR'):
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print("====== ARTIQ IR DUMP ======", file=sys.stderr)
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for function in module.artiq_ir:
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print(function, file=sys.stderr)
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if os.getenv('ARTIQ_DUMP_LLVM'):
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print("====== LLVM IR DUMP ======", file=sys.stderr)
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print(module.build_llvm_ir(target), file=sys.stderr)
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return target.compile_and_link([module]), stitcher.rpc_map
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return target.compile_and_link([module]), stitcher.rpc_map
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except diagnostic.Error as error:
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except diagnostic.Error as error:
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print("\n".join(error.diagnostic.render(colored=True)), file=sys.stderr)
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print("\n".join(error.diagnostic.render(colored=True)), file=sys.stderr)
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