forked from M-Labs/artiq
LLVMIRGenerator: add target data layout to LLVM modules.
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@ -12,6 +12,8 @@ class Target:
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:var triple: (string)
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LLVM target triple, e.g. ``"or1k"``
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:var data_layout: (string)
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LLVM target data layout, e.g. ``"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"``
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:var features: (list of string)
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LLVM target CPU features, e.g. ``["mul", "div", "ffl1"]``
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:var print_function: (string)
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@ -19,6 +21,7 @@ class Target:
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provided by the target, e.g. ``"printf"``.
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"""
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triple = "unknown"
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data_layout = ""
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features = []
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print_function = "printf"
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@ -82,5 +85,6 @@ class NativeTarget(Target):
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class OR1KTarget(Target):
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triple = "or1k-linux"
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data_layout = "E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"
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attributes = ["mul", "div", "ffl1", "cmov", "addc"]
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print_function = "lognonl"
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@ -14,6 +14,7 @@ class LLVMIRGenerator:
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self.llcontext = target.llcontext
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self.llmodule = ll.Module(context=self.llcontext, name=module_name)
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self.llmodule.triple = target.triple
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self.llmodule.data_layout = target.data_layout
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self.llfunction = None
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self.llmap = {}
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self.fixups = []
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