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rtio: fix RTIO/DRTIO timestamp resolution discrepancy

This commit is contained in:
Sebastien Bourdeauducq 2016-11-28 15:01:46 +08:00
parent 9fdd29ddae
commit 85f2467e2c
2 changed files with 5 additions and 12 deletions
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15
artiq/gateware/rtio/core.py
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@ -265,17 +265,10 @@ class LogChannel:
class Core(Module): class Core(Module):
def __init__(self, channels, guard_io_cycles=20): def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
data_width = max(rtlink.get_data_width(c.interface) if fine_ts_width is None:
for c in channels) fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
address_width = max(rtlink.get_address_width(c.interface) for c in channels)
for c in channels)
fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
for c in channels)
self.data_width = data_width
self.address_width = address_width
self.fine_ts_width = fine_ts_width
self.cri = cri.Interface() self.cri = cri.Interface()
self.comb += self.cri.arb_gnt.eq(1) self.comb += self.cri.arb_gnt.eq(1)

2
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -54,7 +54,7 @@ class Master(MiniSoC, AMPSoC):
phy = ttl_simple.Inout(platform.request(sma)) phy = ttl_simple.Inout(platform.request(sma))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_core = rtio.Core(rtio_channels) self.submodules.rtio_core = rtio.Core(rtio_channels, 4)
self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri]) self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
self.submodules.rtio = rtio.KernelInitiator(self.cridec.master) self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)