From 85f2467e2c0d4771a14c69ba9ff3f2591048a5b6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 28 Nov 2016 15:01:46 +0800 Subject: [PATCH] rtio: fix RTIO/DRTIO timestamp resolution discrepancy --- artiq/gateware/rtio/core.py | 15 ++++----------- artiq/gateware/targets/kc705_drtio_master.py | 2 +- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 23fff3039..0f7ef5bed 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -265,17 +265,10 @@ class LogChannel: class Core(Module): - def __init__(self, channels, guard_io_cycles=20): - data_width = max(rtlink.get_data_width(c.interface) - for c in channels) - address_width = max(rtlink.get_address_width(c.interface) - for c in channels) - fine_ts_width = max(rtlink.get_fine_ts_width(c.interface) - for c in channels) - - self.data_width = data_width - self.address_width = address_width - self.fine_ts_width = fine_ts_width + def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20): + if fine_ts_width is None: + fine_ts_width = max(rtlink.get_fine_ts_width(c.interface) + for c in channels) self.cri = cri.Interface() self.comb += self.cri.arb_gnt.eq(1) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index d74b8614f..f1de131cb 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -54,7 +54,7 @@ class Master(MiniSoC, AMPSoC): phy = ttl_simple.Inout(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.submodules.rtio_core = rtio.Core(rtio_channels) + self.submodules.rtio_core = rtio.Core(rtio_channels, 4) self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri]) self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)