forked from M-Labs/artiq
rtio: fix RTIO/DRTIO timestamp resolution discrepancy
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9fdd29ddae
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@ -265,17 +265,10 @@ class LogChannel:
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class Core(Module):
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def __init__(self, channels, guard_io_cycles=20):
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data_width = max(rtlink.get_data_width(c.interface)
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for c in channels)
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address_width = max(rtlink.get_address_width(c.interface)
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for c in channels)
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fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
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for c in channels)
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self.data_width = data_width
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self.address_width = address_width
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self.fine_ts_width = fine_ts_width
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def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
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if fine_ts_width is None:
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fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
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for c in channels)
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self.cri = cri.Interface()
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self.comb += self.cri.arb_gnt.eq(1)
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@ -54,7 +54,7 @@ class Master(MiniSoC, AMPSoC):
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phy = ttl_simple.Inout(platform.request(sma))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.submodules.rtio_core = rtio.Core(rtio_channels, 4)
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self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
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self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)
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