forked from M-Labs/artiq
drtio: fix syntax/import
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d8e9949266
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@ -5,6 +5,7 @@ from migen import *
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from migen.build.generic_platform import *
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from migen.build.generic_platform import *
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from misoc.cores.i2c import *
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from misoc.cores.i2c import *
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from misoc.cores.sequencer import *
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from misoc.cores.sequencer import *
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from misoc.cores import spi as spi_csr
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from misoc.integration.builder import *
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from misoc.integration.builder import *
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from misoc.integration.soc_core import mem_decoder
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from misoc.integration.soc_core import mem_decoder
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from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
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@ -176,13 +177,13 @@ class Satellite(BaseSoC):
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rx_pads=rx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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sys_clk_freq=self.clk_freq)
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ad9154_spi = platform.request("ad9154_spi")
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.csr_devices.append("converter_spi")
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self.csr_devices.append("converter_spi")
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self.config["CONVERTER_SPI_DAC_CS"] = 0
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self.config["CONVERTER_SPI_DAC_CS"] = 0
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self.config["CONVERTER_SPI_CLK_CS"] = 1
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self.config["CONVERTER_SPI_CLK_CS"] = 1
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self.config["HAS_AD9516"] = None
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self.config["HAS_AD9516"] = None
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else:
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else:
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raise ValueError
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raise ValueError
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self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
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self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
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