From 7daab07a29bffa02cf61e28e2f3674d1c9745bcc Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 30 Jan 2017 13:01:45 +0800 Subject: [PATCH] drtio: fix syntax/import --- artiq/gateware/targets/kc705_drtio_satellite.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py index e04df2b61..b402af701 100755 --- a/artiq/gateware/targets/kc705_drtio_satellite.py +++ b/artiq/gateware/targets/kc705_drtio_satellite.py @@ -5,6 +5,7 @@ from migen import * from migen.build.generic_platform import * from misoc.cores.i2c import * from misoc.cores.sequencer import * +from misoc.cores import spi as spi_csr from misoc.integration.builder import * from misoc.integration.soc_core import mem_decoder from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict @@ -176,13 +177,13 @@ class Satellite(BaseSoC): rx_pads=rx_pads, sys_clk_freq=self.clk_freq) - ad9154_spi = platform.request("ad9154_spi") - self.comb += ad9154_spi.en.eq(1) - self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) - self.csr_devices.append("converter_spi") - self.config["CONVERTER_SPI_DAC_CS"] = 0 - self.config["CONVERTER_SPI_CLK_CS"] = 1 - self.config["HAS_AD9516"] = None + ad9154_spi = platform.request("ad9154_spi") + self.comb += ad9154_spi.en.eq(1) + self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) + self.csr_devices.append("converter_spi") + self.config["CONVERTER_SPI_DAC_CS"] = 0 + self.config["CONVERTER_SPI_CLK_CS"] = 1 + self.config["HAS_AD9516"] = None else: raise ValueError self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(