forked from M-Labs/artiq
drtio: initialize AD9516 clock chip
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@ -14,6 +14,9 @@ fn startup() {
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info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
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info!("gateware version {}", board::ident(&mut [0; 64]));
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#[cfg(has_ad9516)]
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board::ad9516::init().expect("cannot initialize ad9516");
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loop {}
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}
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@ -5,6 +5,7 @@ import argparse
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.soc_core import mem_decoder
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from misoc.integration.builder import builder_args, builder_argdict
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@ -59,6 +60,14 @@ class Master(MiniSoC, AMPSoC):
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.csr_devices.append("converter_spi")
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self.config["CONVERTER_SPI_DAC_CS"] = 0
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self.config["CONVERTER_SPI_CLK_CS"] = 1
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self.config["HAS_AD9516"] = None
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else:
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raise ValueError
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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@ -175,6 +175,14 @@ class Satellite(BaseSoC):
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.csr_devices.append("converter_spi")
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self.config["CONVERTER_SPI_DAC_CS"] = 0
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self.config["CONVERTER_SPI_CLK_CS"] = 1
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self.config["HAS_AD9516"] = None
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else:
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raise ValueError
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self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
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