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sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)

This commit is contained in:
Sebastien Bourdeauducq 2018-02-17 17:38:17 +08:00
parent 039dee4c8e
commit 73985a9215
1 changed files with 0 additions and 4 deletions
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4
artiq/gateware/targets/sayma_amc.py
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@ -176,11 +176,7 @@ class Standalone(MiniSoC, AMPSoC):
self.csr_devices.append("serwb_phy_amc") self.csr_devices.append("serwb_phy_amc")
serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep") serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep") serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
serwb_phy_amc.serdes.cd_serwb_serdes.clk, serwb_phy_amc.serdes.cd_serwb_serdes.clk,