From 73985a9215be5b411c37fc6a228b80d45556fe5e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 17 Feb 2018 17:38:17 +0800 Subject: [PATCH] sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed) --- artiq/gateware/targets/sayma_amc.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index eaa1232ac..ab76f9fa5 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -176,11 +176,7 @@ class Standalone(MiniSoC, AMPSoC): self.csr_devices.append("serwb_phy_amc") serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep") - serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk.attr.add("keep") serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep") - platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate), - platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate), - platform.add_period_constraint(serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate) platform.add_false_path_constraints( self.crg.cd_sys.clk, serwb_phy_amc.serdes.cd_serwb_serdes.clk,