forked from M-Labs/artiq
si5324: rename SI5324_FREE_RUNNING to SI5324_AS_SYNTHESIZER
The previous name was causing confusion with the FREE_RUN bit that connects the crystal to CLKIN2.
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cfb21ca126
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@ -89,8 +89,8 @@ fn startup() {
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#[cfg(has_i2c)]
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board_artiq::i2c::init();
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#[cfg(si5324_free_running)]
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setup_si5324_free_running();
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#[cfg(si5324_as_synthesizer)]
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setup_si5324_as_synthesizer();
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#[cfg(has_hmc830_7043)]
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board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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@ -107,8 +107,8 @@ fn startup() {
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}
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}
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#[cfg(si5324_free_running)]
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fn setup_si5324_free_running()
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#[cfg(si5324_as_synthesizer)]
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fn setup_si5324_as_synthesizer()
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{
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// 125MHz output, from 100MHz CLKIN2 reference, 9 Hz
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#[cfg(all(rtio_frequency = "125.0", si5324_ext_ref))]
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@ -229,7 +229,7 @@ class Opticlock(_StandaloneBase):
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def __init__(self, **kwargs):
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_StandaloneBase.__init__(self, **kwargs)
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self.config["SI5324_FREE_RUNNING"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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@ -323,7 +323,7 @@ class Master(MiniSoC, AMPSoC):
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.config["SI5324_FREE_RUNNING"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("sfp_ctl", 2).tx_disable.eq(0)
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@ -292,7 +292,7 @@ class Master(MiniSoC, AMPSoC):
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_FREE_RUNNING"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.transceiver = gth_ultrascale.GTH(
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