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artiq
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firmware: ad9154 timeouts and logging

This commit is contained in:
Sebastien Bourdeauducq 2017-01-03 15:19:51 +01:00
parent 417708af90
commit 6b7e6a53f7
4 changed files with 25 additions and 5 deletions
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3
artiq/firmware/Cargo.lock generated
View File

@ -13,6 +13,9 @@ version = "0.0.0"
[[package]] [[package]]
name = "board" name = "board"
version = "0.0.0" version = "0.0.0"
dependencies = [
"log 0.3.6 (registry+https://github.com/rust-lang/crates.io-index)",
]
[[package]] [[package]]
name = "byteorder" name = "byteorder"

3
artiq/firmware/libboard/Cargo.toml
View File

@ -6,3 +6,6 @@ version = "0.0.0"
[lib] [lib]
name = "board" name = "board"
path = "lib.rs" path = "lib.rs"
[dependencies]
log = { version = "0.3", default-features = false }

21
artiq/firmware/libboard/ad9154.rs
View File

@ -325,7 +325,12 @@ fn dac_setup() -> Result<(), &'static str> {
// 1*ad9154_reg::ENABLE_SERDESPLL | 1*ad9154_reg::RECAL_SERDESPLL) // 1*ad9154_reg::ENABLE_SERDESPLL | 1*ad9154_reg::RECAL_SERDESPLL)
write(ad9154_reg::SERDESPLL_ENABLE_CNTRL, write(ad9154_reg::SERDESPLL_ENABLE_CNTRL,
1*ad9154_reg::ENABLE_SERDESPLL | 0*ad9154_reg::RECAL_SERDESPLL); 1*ad9154_reg::ENABLE_SERDESPLL | 0*ad9154_reg::RECAL_SERDESPLL);
while read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB == 0 {} let t = clock::get_ms();
while read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB == 0 {
if clock::get_ms() > t + 200 {
return Err("SERDES PLL lock timeout");
}
}
write(ad9154_reg::EQ_BIAS_REG, 0x22*ad9154_reg::EQ_BIAS_RESERVED | write(ad9154_reg::EQ_BIAS_REG, 0x22*ad9154_reg::EQ_BIAS_RESERVED |
1*ad9154_reg::EQ_POWER_MODE); 1*ad9154_reg::EQ_POWER_MODE);
@ -421,7 +426,12 @@ fn cfg() -> Result<(), &'static str> {
clock::spin_us(10000); clock::spin_us(10000);
jesd_enable(true); jesd_enable(true);
monitor(); monitor();
while !jesd_ready() {} let t = clock::get_ms();
while !jesd_ready() {
if clock::get_ms() > t + 200 {
return Err("JESD ready timeout");
}
}
clock::spin_us(10000); clock::spin_us(10000);
if read(ad9154_reg::CODEGRPSYNCFLG) != 0x0f { if read(ad9154_reg::CODEGRPSYNCFLG) != 0x0f {
return Err("bad CODEGRPSYNCFLG") return Err("bad CODEGRPSYNCFLG")
@ -444,10 +454,11 @@ fn cfg() -> Result<(), &'static str> {
pub fn init() -> Result<(), &'static str> { pub fn init() -> Result<(), &'static str> {
spi_setup(); spi_setup();
for _ in 0..99 { for i in 0..99 {
let outcome = cfg(); let outcome = cfg();
if outcome.is_ok() { match outcome {
return outcome Ok(_) => return outcome,
Err(e) => warn!("config attempt #{} failed ({}), retrying", i, e)
} }
} }
cfg() cfg()

3
artiq/firmware/libboard/lib.rs
View File

@ -1,6 +1,9 @@
#![feature(asm)] #![feature(asm)]
#![no_std] #![no_std]
#[macro_use]
extern crate log;
use core::{cmp, ptr, str}; use core::{cmp, ptr, str};
include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs")); include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));