From 6b7e6a53f7cbe1d78e6d10d8b3fc0d205d5abf96 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 3 Jan 2017 15:19:51 +0100
Subject: [PATCH] firmware: ad9154 timeouts and logging

---
 artiq/firmware/Cargo.lock          |  3 +++
 artiq/firmware/libboard/Cargo.toml |  3 +++
 artiq/firmware/libboard/ad9154.rs  | 21 ++++++++++++++++-----
 artiq/firmware/libboard/lib.rs     |  3 +++
 4 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/artiq/firmware/Cargo.lock b/artiq/firmware/Cargo.lock
index 61af3ba1e..659180025 100644
--- a/artiq/firmware/Cargo.lock
+++ b/artiq/firmware/Cargo.lock
@@ -13,6 +13,9 @@ version = "0.0.0"
 [[package]]
 name = "board"
 version = "0.0.0"
+dependencies = [
+ "log 0.3.6 (registry+https://github.com/rust-lang/crates.io-index)",
+]
 
 [[package]]
 name = "byteorder"
diff --git a/artiq/firmware/libboard/Cargo.toml b/artiq/firmware/libboard/Cargo.toml
index c006dca4a..b4b992825 100644
--- a/artiq/firmware/libboard/Cargo.toml
+++ b/artiq/firmware/libboard/Cargo.toml
@@ -6,3 +6,6 @@ version = "0.0.0"
 [lib]
 name = "board"
 path = "lib.rs"
+
+[dependencies]
+log = { version = "0.3", default-features = false }
diff --git a/artiq/firmware/libboard/ad9154.rs b/artiq/firmware/libboard/ad9154.rs
index 0edaefa8c..8b999a4cb 100644
--- a/artiq/firmware/libboard/ad9154.rs
+++ b/artiq/firmware/libboard/ad9154.rs
@@ -325,7 +325,12 @@ fn dac_setup() -> Result<(), &'static str> {
     //        1*ad9154_reg::ENABLE_SERDESPLL | 1*ad9154_reg::RECAL_SERDESPLL)
     write(ad9154_reg::SERDESPLL_ENABLE_CNTRL,
             1*ad9154_reg::ENABLE_SERDESPLL | 0*ad9154_reg::RECAL_SERDESPLL);
-    while read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB == 0 {}
+    let t = clock::get_ms();
+    while read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB == 0 {
+        if clock::get_ms() > t + 200 {
+            return Err("SERDES PLL lock timeout");
+        }
+    }
 
     write(ad9154_reg::EQ_BIAS_REG, 0x22*ad9154_reg::EQ_BIAS_RESERVED |
             1*ad9154_reg::EQ_POWER_MODE);
@@ -421,7 +426,12 @@ fn cfg() -> Result<(), &'static str> {
     clock::spin_us(10000);
     jesd_enable(true);
     monitor();
-    while !jesd_ready() {}
+    let t = clock::get_ms();
+    while !jesd_ready() {
+        if clock::get_ms() > t + 200 {
+            return Err("JESD ready timeout");
+        }
+    }
     clock::spin_us(10000);
     if read(ad9154_reg::CODEGRPSYNCFLG) != 0x0f {
         return Err("bad CODEGRPSYNCFLG")
@@ -444,10 +454,11 @@ fn cfg() -> Result<(), &'static str> {
 pub fn init() -> Result<(), &'static str> {
     spi_setup();
 
-    for _ in 0..99 {
+    for i in 0..99 {
         let outcome = cfg();
-        if outcome.is_ok() {
-            return outcome
+        match outcome {
+            Ok(_) => return outcome,
+            Err(e) => warn!("config attempt #{} failed ({}), retrying", i, e)
         }
     }
     cfg()
diff --git a/artiq/firmware/libboard/lib.rs b/artiq/firmware/libboard/lib.rs
index 2a5147b25..eb71c6e25 100644
--- a/artiq/firmware/libboard/lib.rs
+++ b/artiq/firmware/libboard/lib.rs
@@ -1,6 +1,9 @@
 #![feature(asm)]
 #![no_std]
 
+#[macro_use]
+extern crate log;
+
 use core::{cmp, ptr, str};
 
 include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));