forked from M-Labs/artiq
phaser: add note about DDS defines (#650)
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@ -224,6 +224,8 @@ class Phaser(MiniSoC, AMPSoC):
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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# TODO: get rid of those bogus DDS defines
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# currently moninj in the runtime requires them
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 1
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