forked from M-Labs/artiq
shuttler: implement gain & offset register access
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1bb7e9ceef
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67b6588d95
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@ -2,20 +2,47 @@ import numpy
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from artiq.language.core import *
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from artiq.language.core import *
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from artiq.language.types import *
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from artiq.language.types import *
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from artiq.coredevice.rtio import rtio_output
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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class Config:
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class Config:
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kernel_invariants = {"core", "channel", "target_o"}
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kernel_invariants = {
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"core", "channel", "target_base", "target_read",
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"target_gain", "target_offset", "target_clr"
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}
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def __init__(self, dmgr, channel, core_device="core"):
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.core = dmgr.get(core_device)
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self.channel = channel
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self.channel = channel
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self.target_o = channel << 8
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self.target_base = channel << 8
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self.target_read = 1 << 6
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self.target_gain = 0 * (1 << 4)
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self.target_offset = 1 * (1 << 4)
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self.target_clr = 1 * (1 << 5)
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@kernel
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@kernel
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def set_config(self, config):
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def set_clr(self, clr):
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rtio_output(self.target_o, config)
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rtio_output(self.target_base | self.target_clr, clr)
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@kernel
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def set_gain(self, channel, gain):
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rtio_output(self.target_base | self.target_gain | channel, gain)
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@kernel
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def get_gain(self, channel):
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rtio_output(self.target_base | self.target_gain |
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self.target_read | channel, 0)
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return rtio_input_data(self.channel)
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@kernel
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def set_offset(self, channel, offset):
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rtio_output(self.target_base | self.target_offset | channel, offset)
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@kernel
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def get_offset(self, channel):
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rtio_output(self.target_base | self.target_offset |
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self.target_read | channel, 0)
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return rtio_input_data(self.channel)
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class Volt:
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class Volt:
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