forked from M-Labs/artiq
shuttler: support pre-DAC gain & offset
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parent
c02a14ba37
commit
1bb7e9ceef
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@ -100,11 +100,16 @@ class Dac(Module):
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data (Signal[16]): Output value to be send to the DAC.
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clear (Signal): Clear accumulated phase offset when loading a new
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waveform. Input.
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gain (Signal[16]): Output value gain. The gain signal represents the
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decimal part os the gain in 2's complement.
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offset (Signal[16]): Output value offset.
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i (Endpoint[]): Coefficients of the output lines.
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"""
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def __init__(self):
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self.clear = Signal()
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self.data = Signal(16)
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self.gain = Signal(16)
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self.offset = Signal(16)
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###
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@ -113,8 +118,14 @@ class Dac(Module):
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Dds(self.clear),
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]
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# Infer signed multiplication
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data_raw = Signal((14, True))
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data_buf = Signal(14)
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self.sync.rio += [
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self.data.eq(reduce(add, [sub.data for sub in subs])),
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data_raw.eq(reduce(add, [sub.data for sub in subs])),
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# Extra buffer for better DSP timing
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data_buf.eq(((data_raw * Cat(self.gain, ~self.gain[-1])) + (self.offset << 16))[16:]),
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self.data.eq(data_buf),
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]
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self.i = [ sub.i for sub in subs ]
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@ -229,11 +240,43 @@ class Dds(Module):
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class Config(Module):
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def __init__(self):
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self.clr = Signal(16, reset=0xFFFF)
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self.i = Endpoint([("data", 16)])
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self.gain = [ Signal(16) for _ in range(16) ]
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self.offset = [ Signal(16) for _ in range(16) ]
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reg_file = Array(self.gain + self.offset + [self.clr])
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self.i = Endpoint([
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("data", 16),
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("addr", 7),
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])
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self.o = Endpoint([
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("data", 16),
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])
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# This introduces 1 extra latency to everything in config
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# See the latency/delay attributes in Volt & DDS Endpoints/rtlinks
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self.sync.rio += If(self.i.stb, self.clr.eq(self.i.data))
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#
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# Gain & offsets are intended for initial calibration only, latency
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# is NOT adjusted to match outputs to the DAC interface
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#
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# Interface address bits mapping:
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# 6: Read bit. Assert to read, deassert to write.
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# 5: Clear bit. Assert to write clr. clr is write-only.
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# 4: Gain/Offset. (De)Assert to access (Gain)Offset registers.
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# 0-3: Channel selection for the Gain & Offset registers.
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#
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# Reading Gain / Offset register generates an RTIOInput event
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self.sync.rio += [
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self.o.stb.eq(0),
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If(self.i.stb,
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If(~self.i.addr[6],
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reg_file[self.i.addr[:6]].eq(self.i.data),
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).Else(
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# clr register is unreadable, as an optimization
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self.o.data.eq(reg_file[self.i.addr[:5]]),
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self.o.stb.eq(1),
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)
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),
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]
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Phy = namedtuple("Phy", "rtlink probes overrides")
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@ -258,13 +301,23 @@ class Shuttler(Module, AutoCSR):
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self.phys = []
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self.submodules.cfg = Config()
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cfg_rtl_iface = rtlink.Interface(rtlink.OInterface(
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data_width=len(self.cfg.i.data),
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enable_replace=False))
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cfg_rtl_iface = rtlink.Interface(
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rtlink.OInterface(
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data_width=len(self.cfg.i.data),
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address_width=len(self.cfg.i.addr),
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enable_replace=False,
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),
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rtlink.IInterface(
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data_width=len(self.cfg.o.data),
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),
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)
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self.comb += [
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self.cfg.i.stb.eq(cfg_rtl_iface.o.stb),
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self.cfg.i.addr.eq(cfg_rtl_iface.o.address),
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self.cfg.i.data.eq(cfg_rtl_iface.o.data),
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cfg_rtl_iface.i.stb.eq(self.cfg.o.stb),
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cfg_rtl_iface.i.data.eq(self.cfg.o.data),
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]
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self.phys.append(Phy(cfg_rtl_iface, [], []))
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@ -277,6 +330,8 @@ class Shuttler(Module, AutoCSR):
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dac = Dac()
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self.comb += [
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dac.clear.eq(self.cfg.clr[idx]),
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dac.gain.eq(self.cfg.gain[idx]),
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dac.offset.eq(self.cfg.offset[idx]),
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self.dac_interface.data[idx // 2][idx % 2].eq(dac.data)
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]
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@ -13,6 +13,7 @@ from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.rtio.phy import spi2 as rtio_spi
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from artiq.gateware.drtio.transceiver import eem_serdes
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from artiq.gateware.drtio.rx_synchronizer import NoRXSynchronizer
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from artiq.gateware.drtio import *
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@ -145,6 +146,20 @@ class Satellite(BaseSoC, AMPSoC):
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Subsignal('data', Pins('fmc0:HB13_N fmc0:HB12_N fmc0:HB13_P fmc0:HB12_P fmc0:HB15_N fmc0:HB15_P fmc0:HB11_N fmc0:HB09_N fmc0:HB09_P fmc0:HB14_N fmc0:HB14_P fmc0:HB10_N fmc0:HB10_P fmc0:HB11_P')),
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Subsignal('clk', Pins('fmc0:HB06_CC_P')),
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IOStandard('LVCMOS18')),
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('afe_ctrl_dir', 0, Pins('fmc0:LA26_N fmc0:HB00_CC_N fmc0:HB17_CC_P'), IOStandard("LVCMOS18")),
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('afe_ctrl_oe_n', 0, Pins('fmc0:HB19_N'), IOStandard("LVCMOS18")),
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('afe_relay', 0,
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Subsignal('clk', Pins('fmc0:LA02_N')),
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Subsignal('mosi', Pins('fmc0:LA00_CC_N')),
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Subsignal('cs_n', Pins('fmc0:LA02_P fmc0:LA01_CC_N')),
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IOStandard("LVCMOS18")),
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('afe_adc_spi', 0,
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Subsignal('clk', Pins('fmc0:LA29_P')),
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Subsignal('mosi', Pins('fmc0:LA29_N')),
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Subsignal('miso', Pins('fmc0:LA30_N')),
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Subsignal('cs_n', Pins('fmc0:LA28_P')),
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IOStandard("LVCMOS18")),
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('afe_adc_error_n', 0, Pins('fmc0:LA28_N'), IOStandard("LVCMOS18")),
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]
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platform.add_extension(shuttler_io)
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@ -167,6 +182,25 @@ class Satellite(BaseSoC, AMPSoC):
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self.csr_devices.append("shuttler")
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self.rtio_channels.extend(rtio.Channel.from_phy(phy) for phy in self.shuttler.phys)
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afe_dir = platform.request("afe_ctrl_dir")
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self.comb += afe_dir.eq(0b011)
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afe_oe = platform.request("afe_ctrl_oe_n")
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self.comb += afe_oe.eq(0)
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relay_led_phy = rtio_spi.SPIMaster(self.platform.request("afe_relay"))
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self.submodules += relay_led_phy
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print("SHUTTLER RELAY at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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self.rtio_channels.append(rtio.Channel.from_phy(relay_led_phy))
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adc_error_n = platform.request("afe_adc_error_n")
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self.comb += adc_error_n.eq(1)
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adc_spi = rtio_spi.SPIMaster(self.platform.request("afe_adc_spi"))
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self.submodules += adc_spi
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print("SHUTTLER ADC at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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self.rtio_channels.append(rtio.Channel.from_phy(adc_spi))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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