From 3122623c6f9f91e3ce6bfe1335fa273045dfa344 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 12 Mar 2015 13:10:35 +0100 Subject: [PATCH] rtio: make 63-bit timestamp counter the default [soc] --- artiq/gateware/rtio/core.py | 2 +- soc/targets/artiq_ppro.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index b6303d253..eb6b3e2a7 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -294,7 +294,7 @@ class _RTIOBankI(Module): class RTIO(Module, AutoCSR): - def __init__(self, phy, clk_freq, counter_width=32, + def __init__(self, phy, clk_freq, counter_width=63, ofifo_depth=64, ififo_depth=64, guard_io_cycles=20): fine_ts_width = get_fine_ts_width(phy.rbus) diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py index e641b7e3f..5c4d7ff69 100644 --- a/soc/targets/artiq_ppro.py +++ b/soc/targets/artiq_ppro.py @@ -119,6 +119,7 @@ class ARTIQMiniSoC(BaseSoC): output_only_pads=set(rtio_outs)) self.submodules.rtio = rtio.RTIO(self.rtiophy, clk_freq=125000000, + counter_width=32, ififo_depth=512) rtio_csrs = self.rtio.get_csrs()