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gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints

This commit is contained in:
Florent Kermarrec 2017-11-10 10:39:47 +01:00
parent 48bfaec8d3
commit 278c739d30
1 changed files with 10 additions and 9 deletions
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19
artiq/gateware/targets/sayma_rtm.py
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@ -9,6 +9,7 @@ from migen.build.platforms.sinara import sayma_rtm
from misoc.interconnect import wishbone, stream from misoc.interconnect import wishbone, stream
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from misoc.cores import spi from misoc.cores import spi
from misoc.cores import gpio
from misoc.integration.wb_slaves import WishboneSlaveManager from misoc.integration.wb_slaves import WishboneSlaveManager
from misoc.integration.cpu_interface import get_csr_csv from misoc.integration.cpu_interface import get_csr_csv
@ -80,12 +81,12 @@ class SaymaRTM(Module):
self.submodules.rtm_identifier = RTMIdentifier() self.submodules.rtm_identifier = RTMIdentifier()
csr_devices.append("rtm_identifier") csr_devices.append("rtm_identifier")
# clock mux: 125MHz ext SMA clock to HMC830 input # clock mux: 100MHz ext SMA clock to HMC830 input
self.comb += [ self.submodules.clock_mux = gpio.GPIOOut(Cat(
platform.request("clk_src_ext_sel").eq(1), # use ext clk from sma platform.request("clk_src_ext_sel"),
platform.request("ref_clk_src_sel").eq(1), platform.request("ref_clk_src_sel"),
platform.request("dac_clk_src_sel").eq(0), # use clk from dac_clk platform.request("dac_clk_src_sel")))
] csr_devices.append("clock_mux")
self.comb += [ self.comb += [
platform.request("ad9154_rst_n").eq(1), platform.request("ad9154_rst_n").eq(1),
@ -113,9 +114,9 @@ class SaymaRTM(Module):
serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep") serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep")
serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk.attr.add("keep") serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk.attr.add("keep")
serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep") serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 32.0), platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 1.6), platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate),
platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 6.4) platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
serwb_phy_rtm.serdes.cd_serwb_serdes.clk, serwb_phy_rtm.serdes.cd_serwb_serdes.clk,