From 278c739d30fb22435091b56b3f9abe38ffb321f2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Nov 2017 10:39:47 +0100 Subject: [PATCH] gateware/targets/sayma_rtm: add dynamic clock mux, cleanup serwb clock constraints --- artiq/gateware/targets/sayma_rtm.py | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 2a51cd58a..5e0776305 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -9,6 +9,7 @@ from migen.build.platforms.sinara import sayma_rtm from misoc.interconnect import wishbone, stream from misoc.interconnect.csr import * from misoc.cores import spi +from misoc.cores import gpio from misoc.integration.wb_slaves import WishboneSlaveManager from misoc.integration.cpu_interface import get_csr_csv @@ -80,12 +81,12 @@ class SaymaRTM(Module): self.submodules.rtm_identifier = RTMIdentifier() csr_devices.append("rtm_identifier") - # clock mux: 125MHz ext SMA clock to HMC830 input - self.comb += [ - platform.request("clk_src_ext_sel").eq(1), # use ext clk from sma - platform.request("ref_clk_src_sel").eq(1), - platform.request("dac_clk_src_sel").eq(0), # use clk from dac_clk - ] + # clock mux: 100MHz ext SMA clock to HMC830 input + self.submodules.clock_mux = gpio.GPIOOut(Cat( + platform.request("clk_src_ext_sel"), + platform.request("ref_clk_src_sel"), + platform.request("dac_clk_src_sel"))) + csr_devices.append("clock_mux") self.comb += [ platform.request("ad9154_rst_n").eq(1), @@ -113,9 +114,9 @@ class SaymaRTM(Module): serwb_phy_rtm.serdes.cd_serwb_serdes.clk.attr.add("keep") serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk.attr.add("keep") serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk.attr.add("keep") - platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 32.0), - platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 1.6), - platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 6.4) + platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes.clk, 40*1e9/serwb_pll.linerate), + platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_20x.clk, 2*1e9/serwb_pll.linerate), + platform.add_period_constraint(serwb_phy_rtm.serdes.cd_serwb_serdes_5x.clk, 8*1e9/serwb_pll.linerate) platform.add_false_path_constraints( self.crg.cd_sys.clk, serwb_phy_rtm.serdes.cd_serwb_serdes.clk,