forked from M-Labs/artiq
gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8
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59be095512
commit
48bfaec8d3
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@ -13,7 +13,7 @@ from artiq.gateware.serwb.s7phy import S7Serdes
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# 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle pattern.
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# 3) Slave sends K28.5 commas to allow Master to calibrate, Master sends K28.5 commas.
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# 4) Master stops sending K28.5 commas.
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# 5) Slave stops sending K25.5 commas.
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# 5) Slave stops sending K28.5 commas.
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# 6) Link is ready.
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class _SerdesMasterInit(Module):
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@ -120,13 +120,8 @@ class _SerdesMasterInit(Module):
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NextValue(delay_max_found, 0),
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NextState("WAIT_STABLE")
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).Else(
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NextState("RESET_SAMPLING_WINDOW")
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)
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)
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fsm.act("RESET_SAMPLING_WINDOW",
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1),
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NextState("WAIT_SAMPLING_WINDOW"),
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CONFIGURE_SAMPLING_WINDOW",
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@ -246,13 +241,9 @@ class _SerdesSlaveInit(Module, AutoCSR):
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NextValue(delay_max_found, 0),
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NextState("WAIT_STABLE")
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).Else(
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NextState("RESET_SAMPLING_WINDOW")
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)
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)
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fsm.act("RESET_SAMPLING_WINDOW",
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1),
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NextState("WAIT_SAMPLING_WINDOW")
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CONFIGURE_SAMPLING_WINDOW",
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If(delay == (delay_min + (delay_max - delay_min)[1:]),
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@ -368,9 +359,15 @@ class SERWBPLL(Module):
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p_CLKOUT2_DIVIDE=8//vco_div, p_CLKOUT2_PHASE=0.0,
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o_CLKOUT2=pll_serwb_serdes_5x_clk
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),
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Instance("BUFG", i_I=pll_serwb_serdes_clk, o_O=self.serwb_serdes_clk),
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Instance("BUFG", i_I=pll_serwb_serdes_20x_clk, o_O=self.serwb_serdes_20x_clk),
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Instance("BUFG", i_I=pll_serwb_serdes_5x_clk, o_O=self.serwb_serdes_5x_clk)
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Instance("BUFG",
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i_I=pll_serwb_serdes_clk,
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o_O=self.serwb_serdes_clk),
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Instance("BUFG",
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i_I=pll_serwb_serdes_20x_clk,
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o_O=self.serwb_serdes_20x_clk),
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Instance("BUFG",
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i_I=pll_serwb_serdes_5x_clk,
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o_O=self.serwb_serdes_5x_clk)
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]
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self.specials += MultiReg(pll_locked, self.lock)
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