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serwb: replace valid/ready with stb/ack

This commit is contained in:
Florent Kermarrec 2018-04-07 03:06:19 +02:00
parent c8a08375f8
commit 1fd96eb0fd
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/serwb/core.py
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@ -33,16 +33,16 @@ class SERWBCore(Module):
packetizer.source.connect(tx_fifo.sink), packetizer.source.connect(tx_fifo.sink),
tx_fifo.source.connect(scrambler.sink), tx_fifo.source.connect(scrambler.sink),
If(phy.init.ready, If(phy.init.ready,
If(scrambler.source.valid, If(scrambler.source.stb,
phy.serdes.tx_k.eq(scrambler.source.k), phy.serdes.tx_k.eq(scrambler.source.k),
phy.serdes.tx_d.eq(scrambler.source.d) phy.serdes.tx_d.eq(scrambler.source.d)
), ),
scrambler.source.ready.eq(phy.serdes.tx_ce) scrambler.source.ack.eq(phy.serdes.tx_ce)
), ),
# phy --> core # phy --> core
If(phy.init.ready, If(phy.init.ready,
descrambler.sink.valid.eq(phy.serdes.rx_ce), descrambler.sink.stb.eq(phy.serdes.rx_ce),
descrambler.sink.k.eq(phy.serdes.rx_k), descrambler.sink.k.eq(phy.serdes.rx_k),
descrambler.sink.d.eq(phy.serdes.rx_d) descrambler.sink.d.eq(phy.serdes.rx_d)
), ),