forked from M-Labs/artiq
serwb: replace valid/ready with stb/ack
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73b727cade
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@ -53,9 +53,9 @@ class KUSSerdes(Module):
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clk_converter = stream.Converter(40, 8)
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self.submodules += clk_converter
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self.comb += [
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clk_converter.sink.valid.eq(1),
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clk_converter.sink.stb.eq(1),
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clk_converter.sink.data.eq(Replicate(Signal(10, reset=0b1111100000), 4)),
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clk_converter.source.ready.eq(1)
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clk_converter.source.ack.eq(1)
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]
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clk_o = Signal()
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self.specials += [
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@ -80,9 +80,9 @@ class KUSSerdes(Module):
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# tx_data -> encoders -> converter -> serdes
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self.submodules.tx_converter = tx_converter = stream.Converter(40, 8)
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self.comb += [
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tx_converter.sink.valid.eq(1),
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self.tx_ce.eq(tx_converter.sink.ready),
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tx_converter.source.ready.eq(1),
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tx_converter.sink.stb.eq(1),
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self.tx_ce.eq(tx_converter.sink.ack),
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tx_converter.source.ack.eq(1),
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If(self.tx_idle,
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tx_converter.sink.data.eq(0)
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).Else(
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@ -148,8 +148,8 @@ class KUSSerdes(Module):
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# serdes -> converter -> bitslip -> decoders -> rx_data
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self.submodules.rx_converter = rx_converter = stream.Converter(8, 40)
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self.comb += [
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self.rx_ce.eq(rx_converter.source.valid),
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rx_converter.source.ready.eq(1)
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self.rx_ce.eq(rx_converter.source.stb),
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rx_converter.source.ack.eq(1)
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]
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self.submodules.rx_bitslip = rx_bitslip = CEInserter()(BitSlip(40))
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self.comb += rx_bitslip.ce.eq(self.rx_ce)
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@ -195,7 +195,7 @@ class KUSSerdes(Module):
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]
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self.comb += [
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rx_converter.sink.valid.eq(1),
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rx_converter.sink.stb.eq(1),
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rx_converter.sink.data.eq(serdes_q),
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rx_bitslip.value.eq(self.rx_bitslip_value),
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rx_bitslip.i.eq(rx_converter.source.data),
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@ -52,9 +52,9 @@ class S7Serdes(Module):
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clk_converter = stream.Converter(40, 8)
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self.submodules += clk_converter
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self.comb += [
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clk_converter.sink.valid.eq(1),
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clk_converter.sink.stb.eq(1),
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clk_converter.sink.data.eq(Replicate(Signal(10, reset=0b1111100000), 4)),
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clk_converter.source.ready.eq(1)
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clk_converter.source.ack.eq(1)
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]
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clk_o = Signal()
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self.specials += [
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@ -83,9 +83,9 @@ class S7Serdes(Module):
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# tx_data -> encoders -> converter -> serdes
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self.submodules.tx_converter = tx_converter = stream.Converter(40, 8)
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self.comb += [
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tx_converter.sink.valid.eq(1),
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self.tx_ce.eq(tx_converter.sink.ready),
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tx_converter.source.ready.eq(1),
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tx_converter.sink.stb.eq(1),
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self.tx_ce.eq(tx_converter.sink.ack),
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tx_converter.source.ack.eq(1),
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If(self.tx_idle,
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tx_converter.sink.data.eq(0)
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).Else(
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@ -156,8 +156,8 @@ class S7Serdes(Module):
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# serdes -> converter -> bitslip -> decoders -> rx_data
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self.submodules.rx_converter = rx_converter = stream.Converter(8, 40)
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self.comb += [
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self.rx_ce.eq(rx_converter.source.valid),
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rx_converter.source.ready.eq(1)
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self.rx_ce.eq(rx_converter.source.stb),
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rx_converter.source.ack.eq(1)
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]
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self.submodules.rx_bitslip = rx_bitslip = CEInserter()(BitSlip(40))
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self.comb += rx_bitslip.ce.eq(self.rx_ce)
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@ -206,7 +206,7 @@ class S7Serdes(Module):
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]
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self.comb += [
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rx_converter.sink.valid.eq(1),
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rx_converter.sink.stb.eq(1),
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rx_converter.sink.data.eq(serdes_q),
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rx_bitslip.value.eq(self.rx_bitslip_value),
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rx_bitslip.i.eq(rx_converter.source.data),
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