From 1fd96eb0fdfe11a3fa0d74291cfbac4f3862fe28 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 7 Apr 2018 03:06:19 +0200 Subject: [PATCH] serwb: replace valid/ready with stb/ack --- artiq/gateware/serwb/core.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/serwb/core.py b/artiq/gateware/serwb/core.py index a49d7231c..f7e13acd5 100644 --- a/artiq/gateware/serwb/core.py +++ b/artiq/gateware/serwb/core.py @@ -33,16 +33,16 @@ class SERWBCore(Module): packetizer.source.connect(tx_fifo.sink), tx_fifo.source.connect(scrambler.sink), If(phy.init.ready, - If(scrambler.source.valid, + If(scrambler.source.stb, phy.serdes.tx_k.eq(scrambler.source.k), phy.serdes.tx_d.eq(scrambler.source.d) ), - scrambler.source.ready.eq(phy.serdes.tx_ce) + scrambler.source.ack.eq(phy.serdes.tx_ce) ), # phy --> core If(phy.init.ready, - descrambler.sink.valid.eq(phy.serdes.rx_ce), + descrambler.sink.stb.eq(phy.serdes.rx_ce), descrambler.sink.k.eq(phy.serdes.rx_k), descrambler.sink.d.eq(phy.serdes.rx_d) ),