forked from M-Labs/artiq
wrpll: babysit Vivado DSP retiming
Design now passes timing.
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@ -403,10 +403,28 @@ class OpUnit(BaseUnit):
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def __init__(self, op, data_width, stages):
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def __init__(self, op, data_width, stages):
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BaseUnit.__init__(self, data_width)
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BaseUnit.__init__(self, data_width)
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o = op(self.i0, self.i1)
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if stages > 1:
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stb_o = self.stb_i
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# Vivado backward retiming for DSP does not work correctly if DSP inputs
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for i in range(stages):
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# are not registered.
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i0 = Signal.like(self.i0)
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i1 = Signal.like(self.i1)
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stb_i = Signal()
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self.sync += [
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i0.eq(self.i0),
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i1.eq(self.i1),
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stb_i.eq(self.stb_i)
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]
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output_stages = stages - 1
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else:
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i0, i1, stb_i = self.i0, self.i1, self.stb_i
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output_stages = stages
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o = op(i0, i1)
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stb_o = stb_i
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for i in range(output_stages):
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n_o = Signal(data_width)
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n_o = Signal(data_width)
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if stages > 1:
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n_o.attr.add(("retiming_backward", 1))
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n_stb_o = Signal()
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n_stb_o = Signal()
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self.sync += [
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self.sync += [
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n_o.eq(o),
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n_o.eq(o),
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