From 07d43b6e5f4130fbbcab87423ec209b933dfe5d7 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 8 Oct 2020 17:51:27 +0800
Subject: [PATCH] wrpll: babysit Vivado DSP retiming

Design now passes timing.
---
 artiq/gateware/drtio/wrpll/thls.py | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/artiq/gateware/drtio/wrpll/thls.py b/artiq/gateware/drtio/wrpll/thls.py
index f977f2106..b462d9078 100644
--- a/artiq/gateware/drtio/wrpll/thls.py
+++ b/artiq/gateware/drtio/wrpll/thls.py
@@ -403,10 +403,28 @@ class OpUnit(BaseUnit):
     def __init__(self, op, data_width, stages):
         BaseUnit.__init__(self, data_width)
 
-        o = op(self.i0, self.i1)
-        stb_o = self.stb_i
-        for i in range(stages):
+        if stages > 1:
+            # Vivado backward retiming for DSP does not work correctly if DSP inputs
+            # are not registered.
+            i0 = Signal.like(self.i0)
+            i1 = Signal.like(self.i1)
+            stb_i = Signal()
+            self.sync += [
+                i0.eq(self.i0),
+                i1.eq(self.i1),
+                stb_i.eq(self.stb_i)
+            ]
+            output_stages = stages - 1
+        else:
+            i0, i1, stb_i = self.i0, self.i1, self.stb_i
+            output_stages = stages
+
+        o = op(i0, i1)
+        stb_o = stb_i
+        for i in range(output_stages):
             n_o = Signal(data_width)
+            if stages > 1:
+                n_o.attr.add(("retiming_backward", 1))
             n_stb_o = Signal()
             self.sync += [
                 n_o.eq(o),