From 0755757601657785d9ea166eef0d8c8693713fa5 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Mon, 8 Nov 2021 13:00:26 +0800
Subject: [PATCH] compiler/tb: use FPU

---
 artiq/compiler/testbench/perf.py           | 4 ++--
 artiq/compiler/testbench/perf_embedding.py | 4 ++--
 artiq/compiler/testbench/shlib.py          | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/artiq/compiler/testbench/perf.py b/artiq/compiler/testbench/perf.py
index 363c88840..2d70bcf84 100644
--- a/artiq/compiler/testbench/perf.py
+++ b/artiq/compiler/testbench/perf.py
@@ -1,7 +1,7 @@
 import sys, os
 from pythonparser import diagnostic
 from ..module import Module, Source
-from ..targets import RISCVTarget
+from ..targets import RV32GTarget
 from . import benchmark
 
 def main():
@@ -30,7 +30,7 @@ def main():
     benchmark(lambda: Module(source),
               "ARTIQ transforms and validators")
 
-    benchmark(lambda: RISCVTarget().compile_and_link([module]),
+    benchmark(lambda: RV32GTarget().compile_and_link([module]),
               "LLVM optimization and linking")
 
 if __name__ == "__main__":
diff --git a/artiq/compiler/testbench/perf_embedding.py b/artiq/compiler/testbench/perf_embedding.py
index d626d5534..75267cb5b 100644
--- a/artiq/compiler/testbench/perf_embedding.py
+++ b/artiq/compiler/testbench/perf_embedding.py
@@ -5,7 +5,7 @@ from ...master.databases import DeviceDB, DatasetDB
 from ...master.worker_db import DeviceManager, DatasetManager
 from ..module import Module
 from ..embedding import Stitcher
-from ..targets import RISCVTarget
+from ..targets import RV32GTarget
 from . import benchmark
 
 
@@ -45,7 +45,7 @@ def main():
 
     stitcher = embed()
     module = Module(stitcher)
-    target = RISCVTarget()
+    target = RV32GTarget()
     llvm_ir = target.compile(module)
     elf_obj = target.assemble(llvm_ir)
     elf_shlib = target.link([elf_obj])
diff --git a/artiq/compiler/testbench/shlib.py b/artiq/compiler/testbench/shlib.py
index 0aa6386d3..0e2317a5c 100644
--- a/artiq/compiler/testbench/shlib.py
+++ b/artiq/compiler/testbench/shlib.py
@@ -1,7 +1,7 @@
 import sys, os
 from pythonparser import diagnostic
 from ..module import Module, Source
-from ..targets import RISCVTarget
+from ..targets import RV32GTarget
 
 def main():
     if not len(sys.argv) > 1:
@@ -20,7 +20,7 @@ def main():
     for filename in sys.argv[1:]:
         modules.append(Module(Source.from_filename(filename, engine=engine)))
 
-    llobj = RISCVTarget().compile_and_link(modules)
+    llobj = RV32GTarget().compile_and_link(modules)
 
     basename, ext = os.path.splitext(sys.argv[-1])
     with open(basename + ".so", "wb") as f: