2014-05-31 00:20:13 +08:00
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from artiq.language.units import *
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2014-07-11 00:13:37 +08:00
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from artiq.language.core import *
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2014-05-31 00:20:13 +08:00
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2014-06-17 03:39:33 +08:00
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my_range = range
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2014-08-13 18:30:57 +08:00
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class CompilerTest(AutoContext):
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2014-07-11 07:12:40 +08:00
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parameters = "a b A B"
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2014-05-31 00:20:13 +08:00
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2014-06-17 04:56:08 +08:00
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def print_done(self):
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print("Done!")
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2014-06-17 05:51:43 +08:00
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def set_some_slowdev(self, n):
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print("Slow device setting: {}".format(n))
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2014-06-17 04:56:08 +08:00
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2014-05-31 00:20:13 +08:00
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@kernel
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2014-06-17 03:39:33 +08:00
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def run(self, n, t2):
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for i in my_range(n):
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2014-06-17 05:51:43 +08:00
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self.set_some_slowdev(i)
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delay(100*ms)
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2014-05-31 00:20:13 +08:00
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with parallel:
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with sequential:
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2014-06-23 00:52:37 +08:00
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for j in my_range(3):
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self.a.pulse((j+1)*100*MHz, 20*us)
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self.b.pulse(100*MHz, t2)
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2014-05-31 00:20:13 +08:00
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with sequential:
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self.A.pulse(100*MHz, 10*us)
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2014-06-17 03:39:33 +08:00
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self.B.pulse(100*MHz, t2)
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2014-06-17 04:56:08 +08:00
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self.print_done()
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2014-05-31 00:20:13 +08:00
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if __name__ == "__main__":
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2014-07-16 01:20:13 +08:00
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from artiq.devices import corecom_dummy, core, dds_core
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2014-05-31 00:20:13 +08:00
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2014-07-16 01:20:13 +08:00
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coredev = core.Core(corecom_dummy.CoreCom())
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2014-05-31 00:20:13 +08:00
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exp = CompilerTest(
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core=coredev,
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2014-08-13 18:17:08 +08:00
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a=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=0, rtio_channel=0),
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b=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=1, rtio_channel=1),
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A=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=2, rtio_channel=2),
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B=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=3, rtio_channel=3)
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2014-05-31 00:20:13 +08:00
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)
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2014-06-17 03:39:33 +08:00
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exp.run(3, 100*us)
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